Content addressable memory with selective error logging
View Patent ↗A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an error indication according to whether the data value includes an error. An error storage circuit is coupled to receive the error indication from the error detection circuit and is adapted to store an error address that corresponds to the selected storage location if the error indication indicates that the data value includes an error and if the error address is not already stored within the error storage circuit.
1. A content addressable memory (CAM) device comprising:
a plurality of CAM cells;
a plurality of compare lines coupled to the plurality of CAM cells; and
a multiplexer having a first input to receive a first comparand value, a second input to receive a second comparand value, and an output coupled to the plurality of compare lines.
2. The CAM device of claim 1 wherein the first comparand value comprises a match address, and wherein the CAM device further comprises a priority encoder to generate the match address and output the match address to the first input of the multiplexer.
3. The CAM device of claim 1 wherein the second comparand value comprises a first error check address, and wherein the CAM device further comprises an address generator to generate a sequence of error check addresses including the first error check address, the address generator being coupled to a second input of the multiplexer to provide the first error check address thereto.
4. The CAM device of claim 1 wherein the multiplexer is responsive to a comparand select signal to output, as a selected comparand value, either the first comparand value or the second comparand value onto the plurality of compare lines.
5. The CAM device of claim 4 further comprising an instruction decoder to output the comparand select signal in either a first state or a second state to select either the first comparand value or the second comparand value to be output onto the plurality of compare lines.
6. The CAM device of claim 5 wherein the instruction decoder is configured to output the comparand select signal in the second state in response to detecting an unused compare cycle.
7. The CAM device of claim 6 wherein the instruction decoder is further configured to monitor compare instructions received within the CAM device to detect the unused compare cycle.
8. The CAM device of claim 4 further comprising match lines coupled to the plurality of CAM cells, and match logic coupled to the plurality of match lines.
9. The CAM device of claim 8 wherein the match logic is configured to assert a first match signal if any match line of the plurality of match lines indicates a match between a corresponding row of the CAM cells and the selected comparand value.
10. The CAM device of claim 9 further comprising a logic circuit coupled to receive the first match signal and configured to assert a match error signal if the first match signal is asserted and if the selected comparand value that resulted in assertion of the first match signal is the first comparand value.
11. A method of operation within a CAM device, the method comprising:
selecting a first comparand value from a plurality of comparand values in response to a comparand select signal; and
outputting the first comparand value onto compare lines of a first CAM array.
12. The method of claim 11 further comprising generating a match address, and wherein the match address is one of the plurality of comparand values.
13. The method of claim 11 further comprising generating an error check address, and wherein the error check address is one of the plurality of comparand values.
14. The method of claim 11 further comprising generating the comparand select signal in either a first state or a second state based, at least in part, on instructions received from an external device.
15. The method of claim 14 wherein generating the comparand select signal in either a first state or a second state based, at least in part, on instructions received from an external device comprises generating the comparand select signal in the second state in response to detecting an unused compare cycle.
16. The method of claim 15 further comprising monitoring compare instructions received within the CAM device to detect the unused compare cycle.
17. The method of claim 11 further comprising comparing the first comparand value to contents of the first CAM array.
18. The method of claim 17 further comprising asserting a first match signal if the first comparand value matches contents of any rows of CAM cells within the first CAM array.
19. The method of claim 18 further comprising asserting a match error signal if the first match signal is asserted and if the comparand select signal is in a first state.
20. A content addressable memory (CAM) device comprising:
a plurality of CAM cells;
means for selecting a first comparand value from a plurality of comparand values in response to a comparand select signal; and
means for outputting the first comparand value to the plurality of CAM cells.