Method and system for reducing soft-writing in a multi-level flash memory
View Patent ↗A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage, and if the memory cell does not hold the first range of values, to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.
1. A method for reducing soft-writing in a multilevel flash memory during a read operation, the method comprising:
applying a first voltage to a memory cell in the multilevel flash memory and to a first reference cell coupled to the memory cell;
determining, after applying the first voltage, whether the memory cell holds a first range of values;
polarizing a drain of a second reference cell connected to the memory cell while applying the first voltage to the first reference cell, thereby decreasing an amount of time needed to determine whether the memory cell holds a second range of values; and
if the memory cell does not hold the first range of values, then applying a second voltage to the memory cell and to the second reference cell coupled to the memory cell.
2. The method of claim 1 , wherein the second voltage is higher than the first voltage.
3. The method of claim 1 , wherein applying a first voltage to a reference in combination with setting an enable signal allows reading of the multilevel bit with one application of voltage.
4. A method for reducing soft-writing in a multilevel flash memory during a read operation, the method comprising:
applying a first voltage to a memory cell in the multilevel flash memory and to a first reference cell coupled to the memory cell;
determining, after applying the first voltage, whether the memory cell holds a first range of values;
if the memory cell does not hold the first range of values, then applying a second voltage to the memory cell, and to a second reference cell coupled to the memory cell, wherein the second voltage is higher than the first voltage;
determining, after applying the second voltage, whether the memory cell holds a second range of values, wherein the second range of values differs from the first range of values; and
wherein determining whether the memory cell holds a first range of values comprises polarizing a drain of the second reference cell while applying the first voltage to the first reference cell, thereby decreasing an amount of time needed to determine whether the memory cell holds the second range of values.
5. The method of claim 4 , further comprising:
floating the first reference cell while applying the second voltage to the second reference cell.
6. The method of claim 4 , further comprising:
floating the first reference cell while applying the second voltage to the second reference cell.
7. The method of claim 4 , wherein applying a first voltage to a reference in combination with setting an enable signal allows reading of the multilevel bit with one application of voltage.
8. A multilevel flash memory comprising:
a memory cell configured to store a range of values;
a first reference cell and a second reference cell coupled to the memory cell, the first reference cell being configured to receive a first voltage during a read operation and the second reference cell being configured to receive a second voltage during the read operation; and
a current comparison circuit coupled to the first reference cell and the second reference cell and the memory cell, the current comparison circuit configured to
compare current flow through the memory cell with current flow through the first reference cell and the second reference cell,
determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage,
polarize a drain of the second reference cell while the first reference cell is receiving the first voltage, thereby decreasing an amount of time needed to determine whether the memory cell holds the second range of values, and
if the memory cell does not hold the first range of values, the current comparison circuit is further configured to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.
9. The multilevel flash memory of claim 8 , wherein the second voltage is higher than the first voltage.
10. The multilevel flash memory of claim 9 , wherein the second range of values differs from the first range of values.
11. The multilevel flash memory of claim 9 , wherein the memory cell is further configured to receive the first voltage and the second voltage.
12. The multilevel flash memory of claim 8 , wherein the current comparison circuit is further configured to float the first reference cell while the second reference cell is receiving the second voltage.
13. The multilevel flash memory of claim 11 , wherein the current comparison circuit is further configured to float the first reference cell while the second reference cell is receiving the second voltage.
14. The multilevel flash memory of claim 8 , wherein the current comparison circuit includes a number of sense amps corresponding to a number of groups of cells being read.
15. A method for reducing soft-writing in a multilevel flash memory during a read operation comprising:
applying a first voltage to a first reference cell in the multilevel flash memory;
determining, after applying the first voltage, whether a memory cell coupled to the first reference cell holds a first range of values;
if the memory cell does not hold the first range of values, then applying a second voltage to a second reference cell coupled to the memory cell; and
polarizing a drain of the second reference cell while applying the first voltage to the first reference cell, thereby decreasing the amount of time needed to determine whether the memory cell holds the second range of values.
16. The method of claim 15 , wherein the second voltage is higher than the first voltage.
17. The method of claim 16 , further comprising:
determining, after applying the second voltage, whether the memory cell holds a second range of values, wherein the second range of values differs from the first range of values.
18. The method of claim 17 , further comprising floating the first reference cell while applying the second voltage to the second reference cell.
19. The method of claim 15 , wherein applying a first voltage to a reference in combination with setting an enable signal allows reading of the multilevel bit with one application of voltage.
20. A multilevel flash memory comprising:
a memory cell configured to receive a first voltage and a second voltage;
a first reference cell and a second reference cell coupled to the memory cell; and
a current comparison circuit coupled to the first reference cell and the second reference and the memory cell, the current comparison circuit configured to
compare current flow through the memory cell with current flow through the first reference cell and the second reference cell during a read operation,
determine whether the memory cell holds a first range of values while the memory cell receives the first voltage,
polarize a drain of the second reference cell while the memory cell is receiving the first voltage, thereby decreasing an amount of time needed to determine whether the memory cell holds the second range of values, and
if the memory cell does not hold the first range of values, the current comparison circuit is further configured to determine whether the memory cell holds a second range of values while the memory cell receives the second voltage, thereby reducing soft-writing during the read operation.
21. The multilevel flash memory of claim 20 , wherein the second voltage is higher than the first voltage.
22. The multilevel flash memory of claim 21 , wherein the second range of values differs from the first range of values.
23. The multilevel flash memory of claim 22 , wherein the current comparison circuit is further configured to float the first reference cell while the memory cell is receiving the second voltage.
24. The multilevel flash memory of claim 20 , wherein the current comparison circuit includes a number of sense amps corresponding to a number of group of cells being read.