Patent Assignment
Reel/Frame 029090/0922
Security Agreement
Recorded: 2012-10-08
Pages: 34
Assignors
ADESTO TECHNOLOGIES CORPORATION
Executed: 2012-09-27
ARTEMIS ACQUISITION LLC
Executed: 2012-09-27
Assignee
OPUS BANK
19900 MACARTHUR BLVD, 12TH FLOOR, IRVINE, CALIFORNIA, 92612
Covered Properties
(97)
Low power voltage regulator circuit for use in an integrated circuit device
Patent:
6,320,454 →
Application:
09/586,664 →
Reference cell for high speed sensing in non-volatile memories
Patent:
6,411,549 →
Application:
09/602,108 →
Row Decoder Circuit for Use in Programming a Memory Device
Patent:
6,621,745 →
Application:
10/174,632 →
Method of Programming a Multi-Level Memory Device
Method of Establishing Reference Levels for Sensing Multilevel Memory Cell States
Patent:
6,618,297 →
Application:
10/211,437 →
Method of Recovering Overerased Bits in a Memory Device
Method for Identification of Spi Compatible Serial Memory Devices
Current Sense Amplifier
Dual Stage Voltage Regulation Circuit
Method and Apparatus of a Smart Decoding Scheme for Fast Synchronous Read in a Memory System
Functional Register Decoding System for Multiple Plane Operation
Memory System and Process for Controlling a Memory Component to Achieve Different Kinds of Memory Characteristics on One and the Same Memory Component
Approach for Zero Dummy Byte Flash Memory Read Operation
Patent:
6,879,535 →
Application:
10/929,899 →
Method for Fabricating a Semiconductor Memory Cell
Method for Manufacturing an Integrated Circuit Including an Electrolyte Material Layer
Resistively Switching Memory
Semiconductor Memory Component in Cross-Point Architecture
Redundant Column Read in a Memory Array
Method for Operating an Integrated Circuit Having a Resistivity Changing Memory Cell
Method and System for Reducing Soft-Writing in a Multi-Level Flash Memory
Method for Producing Memory Having a Solid Electrolyte Material Region
Channel Discharging After Erasing Flash Memory Devices
Method for Fabricating an Integrated Device Comprising a Structure with a Solid Electrolyte
A Memory Device Including Electrical Circuit Configured to Provide Reversible Bias Across the Pmc Memory Cell to Perform Erase and Write Functions
Memory Having Cbram Memory Cells and Method
Memory Component with Memory Cells Having Changeable Resistance and Fabrication Method Therefor
Resistive Memory Arrangement
Method for Manufacturing a Cbram Semiconductor Memory
Method for Improving the Thermal Characteristics of Semiconductor Memory Cells
Read, Write and Erase Circuit for Programmable Memory Devices
Column/Sector Redundancy Cam Fast Programming Scheme Using Regular Memory Core Array in Multi-Plane Flash Memory Device
Patent:
7,196,952 →
Application:
11/295,878 →
Pmc Memory Circuit and Method for Storing a Datum in a Pmc Memory Circuit
Integrated Semiconductor Memory with an Arrangement of Nonvolatile Memory Cells, and Method
Method for Fabricating a Resistive Memory
Resistive Memory Element with Shortened Erase Time
Solid Electrolyte Memory Element and Method for Fabricating Such a Memory Element
Memory Cell, Memory Device and Method for the Production Thereof
Integrated Circuit Including Resistivity Changing Memory Cells
Memory Cells with an Anode Comprising Intercalating Material and Metal Species Dispersed Therein
Cbram Cell and Cbram Array, and Method of Operating Thereof
Method for Fabricating a Solid Electrolyte Memory Device and Solid Electrolyte Memory Device
Voltage Reference Circuit Using Programmable Metallization Cells
Method for Preventing Over-Erasing of Unused Column Redundant Memory Cells in a Flash Memory Having Single-Transistor Memory Cells
Programmable Memory Device Circuit
Device and Method for Access Time Reduction by Speculatively Decoding Non-Memory Read Commands on a Serial Interface
Implementation of Column Redundancy for a Flash Memory with a High Write Parallelism
Resistive Memory Arrangement
Methods of Manufacturing a Semiconductor Device; Method of Manufacturing a Memory Cell; Semiconductor Device; Semiconductor Processing Device; Integrated Circuit Having a Memory Cell
Integrated Circuit, Method for Manufacturing an Integrated Circuit, Memory Cell Array, Memory Module, and Device
Nor and Nand Memory Arrangement of Resistive Memory Elements
Resistive Switching Element
Application:
11/746,393 →
Publication:
US 2008/0278988
Method of Manufacturing an Integrated Circuit, an Integrated Circuit, and a Memory Module
Read, Write, and Erase Circuit for Programmable Memory Devices
A Memory Device Including Electrical Circuit Configured to Provide Reversible Bias Across the Pmc Memory Cell to Perform Erase and Write Functions
Method and System to Access Memory
Integrated Circuits Having Programmable Metallization Cells (Pmcs) and Operating Methods Therefor
Patent:
8,107,273 →
Application:
12/508,212 →
Variable Impedance Memory Device Having Simultaneous Program and Erase, and Corresponding Methods and Circuits
Patent:
8,274,842 →
Application:
12/566,790 →
Reconfigurable Memory Arrays Having Programmable Impedance Elements and Corresponding Methods
Patent:
8,331,128 →
Application:
12/629,531 →
Conducting Bridge Random Access Memory (CBRAM) Device Structures
Patent:
8,426,839 →
Application:
12/767,552 →
Pmc-Based Non-Volatile Cam
Patent:
8,320,148 →
Application:
12/802,506 →
Method for Producing Memory Having a Solid Electrolyte Material Region
Methods and Circuits for Temperature Varying Write Operations of Programmable Impedance Elements
Patent:
8,437,171 →
Application:
12/980,752 →
Method and System to Access Memory
Circuits and Methods Having Programmable Impedance Elements
Patent:
8,947,913 →
Application:
13/114,192 →
Circuits Having Programmable Impedance Elements
Patent:
8,687,403 →
Application:
13/157,713 →
Variable Impedance Memory Device Structure and Method of Manufacture Including Programmable Impedance Memory Cells and Methods of Forming the Same
Patent:
8,829,482 →
Application:
13/242,854 →
Read Methods, Circuits and Systems for Memory Devices
Patent:
8,654,561 →
Application:
13/276,763 →
Memory Devices, Circuits and Methods Having Data Values Based on Dynamic Change in Material Property
Patent:
9,177,639 →
Application:
13/315,652 →
Resistive Memory Devices, Circuits and Methods Having Read Current Limiting
Patent:
9,165,648 →
Application:
13/336,642 →
Methods of Programming and Erasing Programmable Metallization Cells (Pmcs)
Patent:
8,369,132 →
Application:
13/337,004 →
Memory Cell Device and Method of Manufacture
Memory Devices and Methods for Read and Write Operation to Memory Elements Having Dynamic Change in Property
Patent:
9,099,175 →
Application:
13/408,367 →
Read Operations and Circuits for Memory Devices Having Programmable Elements, Including Programmable Resistance Elements
Patent:
8,913,444 →
Application:
13/408,797 →
Programmable Impedance Memory Elements, Methods of Manufacture, and Memory Devices Containing the Same
Patent:
8,847,191 →
Application:
13/431,951 →
Circuits and Methods for Placing Programmable Impedance Memory Elements in High Impedance States
Patent:
8,730,752 →
Application:
13/437,906 →
Variable Impedance Memory Element Structures, Methods of Manufacture, and Memory Devices Containing the Same
Patent:
8,624,219 →
Application:
13/445,389 →
Resistive Switching Memories
Patent:
9,029,829 →
Application:
13/462,659 →
Conductive Filament Based Memory Elements and Methods with Improved Data Retention and/or Endurance
Memory Devices, Architectures and Methods for Memory Elements Having Dynamic Change in Property
Patent:
8,854,873 →
Application:
13/464,926 →
Method of Operating a Resistive Memory Device with a Ramp-Up/Ramp-Down Program/Erase Pulse
Contact Structure and Method for Variable Impedance Memory Element
Erase and Soft Program Within the Erase Operation for a High Speed Resistive Switching Memory Operation with Controlled Erased States
Patent:
8,659,931 →
Application:
13/488,392 →
Resistive Switching Devices Having A Buffer Layer and Methods of Formation Thereof
Patent:
8,866,122 →
Application:
13/517,653 →
METHODS OF PROGRAMMING AND ERASING PROGRAMMABLE METALLIZATION CELLS (PMCs)
Patent:
8,625,331 →
Application:
13/545,792 →
Programmable Memory Elements, Devices and Methods Having Physically Localized Structure
Patent:
8,895,953 →
Application:
13/545,958 →
Programmable Window of Operation for Cbram
Patent:
9,047,948 →
Application:
13/548,429 →
Cbram/Reram with Improved Program and Erase Algorithms
Patent:
8,659,954 →
Application:
13/548,470 →
Resistive Switching Devices Having Alloyed Electrodes And Methods of Formation Thereof
Ag-Alloy Top Electrode for Improved Cbram Performance
Application:
61/534,011 →
Dynamic Memory with Programmable Impedance Shadow Elements
Application:
61/540,539 →
Circuits and Methods for Programming Variable Impedance Elements
Application:
61/589,251 →
Pre-Conditioning Programmable Impedance Elements in Memory Devices
Application:
61/596,671 →
Semiconductor Devices and Methods of Formation Thereof
Application:
61/601,942 →
Solid Electrolyte Memory Elements with Electrode Interface for Improved Performance
Application:
61/615,837 →
Memory Devices and Methods Having Adaptable Read Threshold Levels
Application:
61/616,064 →
Programmed/Triggered Cell Annihilation for Resistive Switching Memory Devices
Application:
61/636,800 →
Low Power System Architecture Using Cbram
Application:
61/647,064 →
Related Assignments
(10)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 10, 2013
From: ATMEL CORPORATION
To: ARTEMIS ACQUISITION LLC
Reel/Frame 029605/0665 →
Security Agreement
Oct 7, 2013
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: BRIDGE BANK, NATIONAL ASSOCIATION
Reel/Frame 031371/0581 →
Release of Security Interest
Oct 15, 2013
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 031414/0232 →
Security Interest
May 22, 2015
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 035754/0580 →
Release of Security Interest
Oct 3, 2017
From: WESTERN ALLIANCE BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 044219/0610 →
Security Interest
May 8, 2018
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
Reel/Frame 046105/0731 →
Release of Security Interest
May 9, 2019
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 049125/0970 →
Release of Security Interest
Sep 24, 2019
From: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 050480/0836 →
Release of Security Interest
Jul 12, 2022
From: VENTURE LENDING & LEASING IX, INC.; WTI FUND X, INC.
To: PARALLEL WIRELESS, INC.
Reel/Frame 060900/0022 →
Assignment of Assignor's Interest
Mar 16, 2023
From: RENESAS DESIGN US INC. (FORMERLY KNOWN AS DIALOG SEMICONDUCTOR US INC. AS SUCCESSOR-IN-INTEREST TO ADESTO TECHNOLOGIES CORPORATION AND ARTEMIS ACQUISITION, LLC)
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 062999/0839 →