Granted Patent B2

US 7,538,411 · App. 11/411,994 · Granted May 26, 2009

Abstract

Claims (58)

1. An integrated circuit, comprising:

a substrate comprising a surface;

wordline stacks arranged parallel at a distance from one another on the surface;

bitlines arranged transversely to the wordlines at a distance from one another;

source/drain regions formed as doped regions in the vicinity of the wordline stacks;

a layer sequence comprising a bottom electrode layer, a resistive layer, and an upper electrode layer disposed between a plurality of the source/drain regions and the bitlines, wherein the resistive layer is disposed in a plane that is vertical to the substrate surface and at least a part of the resistive layer is disposed in a recess of the substrate surface;

the upper electrode layer comprising separate sections;

the bottom electrode layer comprising separate sections corresponding to the sections of the upper electrode layer;

a bitline connecting a plurality of sections of the upper electrode layer; and

source lines arranged parallel to the wordline stacks, the source lines connecting further pluralities of the source/drain regions.

2. The integrated circuit according to claim 1 , wherein the resistive layer comprises separate sections, every section being covered by one of the bitlines.

3. The integrated circuit according to claim 1 , wherein the resistive layer comprises a transition metal oxide.

4. The integrated circuit according to claim 1 , wherein the resistive layer comprises a solid-state electrolyte.

5. The integrated circuit according to claim 1 , wherein the resistive layer comprises an organic material.

6. The integrated circuit according to claim 1 , wherein the source lines comprise a source line layer of electrically conductive material.

7. The integrated circuit according to claim 6 , wherein the source lines are arranged in self-aligned fashion with respect to the wordline stacks.

8. A method of production of resistive memory devices, comprising:

providing a substrate of semiconductor material comprising a surface;

forming wordline stacks on the surface, the wordline stacks being arranged parallel to one another and at a distance from one another to form interspaces;

forming doped regions in the substrate in the vicinity of the wordline stacks;

forming recesses in the substrate in every second interspace between the wordline stacks;

applying a resistive layer on the doped regions and providing an electric connection between the resistive layer and the doped regions;

applying an electrically conductive material filling the recesses; and

structuring the electrically conductive material to form bitlines running transversely to the wordline stacks.

9. The method according to claim 8 , wherein

the resistive layer is formed from a transition metal oxide.

10. The method according to claim 8 , wherein

the resistive layer is formed from a solid-state electrolyte.

11. The method according to claim 8 , wherein

the resistive layer is formed from an organic material.

12. The method according to claim 8 , further comprising:

forming parallel shallow trench isolations in the substrate, the shallow trench isolations comprising longitudinal extensions transversely to the wordline stacks.

13. The method according to claim 8 , wherein

the doped regions are formed to comprise source/drain regions and source lines.

14. The method according to claim 8 , further comprising:

applying a further layer of electrically conductive material to form source lines connecting pluralities of the doped regions.

15. The method according to claim 13 , wherein the source lines are formed in self-aligned fashion with respect to the wordline stacks.

16. The method according to claim 14 , wherein the source lines are formed in self-aligned fashion with respect to the wordline stacks.

17. A method of production of resistive memory devices, comprising:

providing a substrate of semiconductor material comprising a surface;

forming parallel wordline stacks on the surface comprising interspaces between the wordline stacks;

forming doped regions in the substrate in the vicinity of the wordline stacks;

forming recesses in the substrate in every second interspace between the wordline stacks;

applying a bottom layer of an electrically conductive material on the doped regions within the recesses;

applying a resistive layer on the bottom layer;

applying an upper layer of an electrically conductive material on the resistive layer;

applying a further electrically conductive material on the upper layer, filling the recesses; and

structuring the further electrically conductive material, the upper layer, the resistive layer, and the bottom layer to form bitlines and resistive memory cells.

18. An integrated circuit, comprising:

a substrate comprising a surface;

wordline stacks arranged parallel at a distance from one another on the surface;

bitlines arranged transversely to the wordlines at a distance from one another;

source/drain regions formed as doped regions in the vicinity of the wordline stacks; a layer sequence comprising a bottom electrode layer, a resistive layer, and an upper electrode layer disposed between a plurality of the source/drain regions and the bitlines;

the upper electrode layer comprising separate sections;

the bottom electrode layer comprising separate sections corresponding to the sections of the upper electrode layer;

a bitline connecting a plurality of sections of the upper electrode layer; and

source lines arranged parallel to the wordline stacks, the source lines connecting further pluralities of the source/drain regions,

wherein at least a part of the resistive layer is disposed in a recess of the substrate surface.

Assignments (12)