Granted Patent B2

US 7,372,716 · App. 11/209,424 · Granted May 13, 2008

Abstract

Claims (30)

1. A memory cell arrangement comprising:

a plurality of memory cells of a CBRAM type;

a programming apparatus, the memory cells being arranged along bit lines, each bit line having a programming apparatus, the programming apparatus having a charge storage device and a switchable charging apparatus, wherein the switchable charging apparatus has a charging transistor and a plurality of selection transistors.

2. The memory cell arrangement of claim 1 , comprising:

wherein the programming apparatus includes a connection for a programming potential.

3. The memory cell arrangement of claim 1 , comprising:

wherein the charging transistor is configured to be switched using a charging signal.

4. The memory cell arrangement of claim 2 , comprising wherein a respective one of the selection transistors is part of a respective memory cell.

5. The memory cell arrangement of claim 1 , comprising wherein a respective one of the selection transistors can be selected using a word line.

6. A memory cell arrangement comprising:

a plurality of memory cells of a CBRAM type;

a programming apparatus, the memory cells being arranged along bit lines, each bit line having a programming apparatus, the programming apparatus having a charge storage device and a switchable charging apparatus, wherein the switchable charging apparatus has a charging transistor and a plurality of selection transistors; wherein the bit lines inherently each have a bit line capacitance, and wherein the charge storage device associated with a bit line is formed from the bit line capacitance and a charge capacitance.

7. The memory cell arrangement of claim 6 , comprising wherein one connection of the charge capacitance is connected to a reference-ground potential.

8. The memory cell arrangement of claim 7 , comprising wherein the reference-ground potential is a potential whose value is fixed.

9. The memory cell arrangement of claim 7 , comprising wherein the reference-ground potential is a potential whose value can be changed.

10. A method for programming memory cells of the CBRAM type, comprising:

storing a given quantity of an electrical charge in a charge storage device; and

transferring the stored quantity of electrical charge to a memory cell to be programmed, thereby

using a charging signal to electrically turn on a charging transistor at a first point in time, with the result that the charge storage device is electrically connected to a programming potential in order to be charged, and

wherein the charging transistor is electrically turned off again at a second point in time when the charge storage device has the given quantity of electrical charge.

11. The method of claim 10 , comprising:

transferring the quantity of electrical charge stored in the charge storage device to the memory cell as of a third point in time.

12. The method of claim 10 , comprising:

wherein after the second point in time, raising the potential at which the bit line currently lies using charge displacement.

13. A method for programming memory cells of the CBRAM type, comprising:

storing a given quantity of an electrical charge in a charge storage device;

using a charging signal to electrically turn on a charging transistor at a first point in time, with the result that the charge storage device is electrically connected to a programming potential in order to be charged, and wherein the charging transistor is electrically turned off again at a second point in time when the charge storage device has the given quantity of electrical charge; and

transferring the stored quantity of electrical charge to a memory cell to be programmed, including transferring the quantity of electrical charge stored in the charge storage device to the memory cell as of a third point in time.

14. The method of claim 13 , comprising:

wherein after the second point in time, raising the potential at which the bit line currently lies using charge displacement.

Assignments (9)