NOR and NAND memory arrangement of resistive memory elements
View Patent ↗A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.
1. A NOR memory arrangement comprising a plurality of resistive memory elements, each memory element comprising:
a resistive memory cell comprising a resistive memory material; and
a MOS memory cell selection transistor connected in series, via a source-drain path of the selection transistor, to the resistive memory cell;
wherein each memory element is connected via the source-drain path of the selection transistor to a first current line that applies a reference voltage, each memory element is connected via the resistive memory cell to a second current line that applies an operating voltage, each memory element is connected to a third current line via a gate terminal of the MOS memory cell selection transistor, the first current line is disposed at a location between the second current line and the third current line, the first and third current lines extend in directions that are transverse a direction in which the second current line extends, and at least an isolation layer separates neighboring second current lines.
2. The memory arrangement of claim 1 , wherein the first current line extends in a direction parallel to the third current line.
3. The memory arrangement of claim 1 , wherein the first current line is grounded.
4. The memory arrangement of claim 1 , wherein each memory cell has a memory cell area of less than 9 F 2 .
5. The memory arrangement of claim 1 , wherein each memory cell has a memory cell area within the range of 5 F 2 to 6 F 2 .
6. The memory arrangement of claim 1 , wherein the resistive memory material comprises copper.