IP Library Granted Patent US 8,895,953
Granted Patent B1
US 8,895,953 · App. 13/545,958 · Granted Nov 25, 2014

Programmable memory elements, devices and methods having physically localized structure

Inventors: Jeffrey Allan Shields (Sunnyvale, CA); John Ross Jameson (Burlingame, CA); Wei Ti Lee (San Jose, CA)
Assignee: Adesto Technologies Corporation
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Quick Facts
Patent No.
US 8,895,953
App. No.
13/545,958
Granted
Nov 25, 2014
Kind
B1
Abstract

A programmable memory element can include an insulating layer formed over a bottom structure; an opening formed in the insulating layer; a sidewall structure formed next to side surfaces of the opening; a tapered structure formed within the opening adjacent to the sidewall structure; and a solid electrolyte forming at least a portion of a structure selected from: the bottom structure, the sidewall structure, and the tapered structure.

Claims (13)

1. A programmable memory element, having at least one localized element structure, comprising:

at least an anode electrode, solid electrolyte, and cathode electrode aligned with one another along a substantially vertical axis; wherein

at least one of the electrodes includes a tapered structure having a wide portion that tapers to a narrow portion in the vertical axis direction, and

the anode electrode is formed from at least one element oxidizable to ion conduct in the solid electrolyte; wherein the tapered structure forms at least part of the anode electrode and is formed within an opening having a sidewall structure formed thereon,

the solid electrolyte is formed below the opening, and

the cathode electrode is formed below the solid electrolyte.

2. The programmable memory element of claim 1 , wherein:

the tapered structure is formed within an opening having a sidewall structure formed thereon, the sidewall structure comprises a different material than the tapered structure.

3. The programmable memory element of claim 1 , wherein:

the solid electrolyte is selected from: a chalcogenide and a metal oxide.

4. The programmable memory element of claim 1 , further including:

the tapered structure comprises at least a portion of the anode electrode and is separated from the solid electrolyte by a void region; wherein

a conductive path through the void region is formed and dissolved by application of electric fields.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2023
From: RENESAS DESIGN US INC. (FORMERLY KNOWN AS DIALOG SEMICONDUCTOR US INC. AS SUCCESSOR-IN-INTEREST TO ADESTO TECHNOLOGIES CORPORATION AND ARTEMIS ACQUISITION, LLC)
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 063118/0352 →
RELEASE OF SECURITY INTEREST Recorded Sep 24, 2019
From: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 050480/0836 →
RELEASE OF SECURITY INTEREST Recorded May 9, 2019
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 049125/0970 →
SECURITY INTEREST Recorded May 8, 2018
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
Reel/Frame 046105/0731 →
SECURITY INTEREST Recorded May 22, 2015
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 035754/0580 →
RELEASE OF SECURITY INTEREST Recorded Oct 15, 2013
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 031414/0232 →
SECURITY AGREEMENT Recorded Oct 8, 2012
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 029090/0922 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2012
From: SHIELDS, JEFFREY ALLAN; JAMESON, JOHN ROSS; LEE, WEI TI
To: ADESTO TECHNOLOGIES CORPORATION
Reel/Frame 029015/0331 →
Continuity (1)
Provisional Application 61508334 · Jul 15, 2011