Method and system to access memory
View Patent ↗This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.
1. A system comprising:
a host controller;
an Input/Output (I/O) buffer; and
a memory device coupled to the host controller and configured to receive a read command from the host controller, the memory device including an interface control logic in communication with a memory array;
wherein the interface control logic includes a latency programming circuit coupled to the memory array and the I/O buffer, the latency programming circuit to store at least one value corresponding to a delay to be provided at the memory array prior to transferring data from the memory array during a read operation, and the latency programming circuit configured to provide the delay by incrementing a counter after a number of clock cycles and by comparing the counter with the value corresponding to the delay.
2. The system of claim 1 , wherein the latency programming circuit comprises a programmable latency register to store the at least one value corresponding to the delay.
3. The system of claim 2 , wherein the memory array includes a FLASH memory.
4. The system of claim 1 , wherein the at least one value corresponding to the delay is associated with a number of dummy bytes required to provide the delay.
5. The system of claim 4 , wherein the at least one value corresponding to the number of dummy bytes is hardwired using blow-out fuses.
6. The system of claim 4 , wherein the at least one value corresponding to the number of dummy bytes is provided in a look-up table.
7. A method of performing a read operation in a memory device, comprising:
storing a plurality of values corresponding to dummy byte delays associate with at least one read operation;
sending a read command to the memory device;
waiting for a time period corresponding to a dummy byte delay for a read command by incrementing a counter after a number of clock cycles and comparing the counter with the value corresponding to the delay; and
initiating a transfer of data from the memory device.
8. The method of claim 7 , wherein storing the plurality of values includes storing the plurality of values corresponding to the dummy byte delays to be received at the memory device.
9. The method of claim 7 , wherein storing the plurality of values corresponding to the dummy byte delays includes storing the plurality of values corresponding to the dummy byte delays in a non-volatile memory.
10. The method of claim 7 , wherein storing the plurality of values corresponding to the dummy byte delays includes storing the plurality of values corresponding to the dummy byte delays in a look-up table.
11. The method of claim 7 , wherein storing the plurality of values of dummy byte delays includes storing the plurality of dummy byte delays associated with a plurality of operational codes used for a read operation.