IP Library Granted Patent US 7,368,314
Granted Patent B2
US 7,368,314 · App. 11/344,533 · Granted May 6, 2008

Method for fabricating a resistive memory

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Quick Facts
Patent No.
US 7,368,314
App. No.
11/344,533
Granted
May 6, 2008
Kind
B2
Abstract

A method for fabricating a resistively switching memory cell is provided. The method includes the following steps: depositing a first electrode, applying a layer of a chalcogenide compound to the first electrode, applying a layer of silver or copper, and operating a noble gas plasma in a back-sputtering mode in order to effect silver or copper diffusion into the layer of the chalcogenide compound. Optionally, and if appropriate, further layers for the second electrode are then deposited.

Claims (33)

1. A method for fabricating a resistively switching memory cell, the method comprising the following sequential steps:

depositing a first electrode;

applying a layer comprising a chalcogenide compound to the first electrode;

applying on the layer of the chalcogenide compound a metallic doping layer comprising one of silver and copper in an argon gas plasma; and then

performing an additional step of diffusion of the metal from the doping layer into the layer of the chalcogenide compound through a back-sputtering process in a xenon gas plasma.

2. The method of claim 1 , further comprising depositing a second electrode comprising at least one layer of copper, silver and a silver alloy.

3. The method of claim 2 , wherein the second electrode consists of silver.

4. The method of claim 1 , wherein the chalcogenide compound comprises one of a binary germanium sulfide compound, a germanium selenide compound and a ternary or quaternary composition made up of Ge, Si, Se and S.

5. The method of claim 4 , wherein the germanium sulfide compound has the formula Ge x S 1-x , the germanium selenide compound has the formula Ge x Se 1-x , and x has a value from 0.2 to 0.5.

6. The method of claim 5 , wherein x is 0.33.

7. The method of claim 1 , wherein the first electrode comprises an electrically conductive, inert material.

8. The method of claim 7 , wherein the first electrode consists of a material selected from the group consisting of tungsten, molybdenum, tantalum, titanium, conductive oxides, conductive nitrides, highly doped n-typed silicon compounds, highly doped p-type silicon compounds, and combinations thereof.

9. The method of claim 8 , wherein the first electrode consists of tungsten.

10. The method of claim 1 , wherein a voltage applied to the substrate in the back-sputtering process is within a range from about −200V to about −400V.

11. The method of claim 10 , wherein the voltage applied to the substrate in the back-sputtering process is about −400V.

12. The method of claim 1 , wherein a vacuum used in the back-sputtering process is within a range from 4×10 −3 mbar to 10×10 −3 mbar.

13. The method of claim 1 , wherein the back-sputtering process is performed for a period of time lasting from 5 minutes to 10 minutes.

14. A method for fabricating a resistive memory, the method comprising:

depositing a first electrode;

depositing a resistivity changing material contacting the first electrode;

depositing a metallic doping material comprising one of silver and copper in a noble gas plasma over the resistivity changing material; and

performing a diffusion of the metallic, doping material into the resistivity changing material via a back-sputtering process in a xenon gas plasma.

15. The method of claim 14 , further comprising depositing a second electrode comprising at least one of copper, silver, and a silver alloy over the resistivity changing material.

16. The method of claim 14 , wherein a voltage applied to the substrate in the back-sputtering process is within a range from −200V to −400V.

17. The method of claim 14 , wherein the first electrode comprises an electrically conductive and inert material.

18. The method of claim 14 , wherein the back-sputtering process is performed for a period lasting from 5 minutes to 10 minutes.

19. The method of claim 14 , wherein depositing the resistivity changing material comprises depositing a chalcogenide compound.

20. A method for fabricating a resistively switching memory, the method comprising:

depositing a first electrode comprising an electrically conductive and inert material;

applying a layer comprising a chalcogenide compound to the first electrode;

applying a metallic doping layer comprising one of silver and copper in an argon gas plasma to the layer of the chalcogenide compound;

performing a diffusion of the metal from the doping layer into the layer of the chalcogenide compound through a back-sputtering process in a xenon gas plasma; and

depositing a second electrode comprising at least one of copper, silver, and a silver alloy over the chalcogenide compound.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Sep 24, 2019
From: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 050480/0836 →
RELEASE OF SECURITY INTEREST Recorded May 9, 2019
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 049125/0970 →
SECURITY INTEREST Recorded May 8, 2018
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
Reel/Frame 046105/0731 →
RELEASE OF SECURITY INTEREST Recorded Oct 3, 2017
From: WESTERN ALLIANCE BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 044219/0610 →
SECURITY INTEREST Recorded May 22, 2015
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 035754/0580 →
RELEASE OF SECURITY INTEREST Recorded Oct 15, 2013
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 031414/0232 →
SECURITY AGREEMENT Recorded Oct 7, 2013
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: BRIDGE BANK, NATIONAL ASSOCIATION
Reel/Frame 031371/0581 →
SECURITY AGREEMENT Recorded Oct 8, 2012
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 029090/0922 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2010
From: QIMONDA AG
To: ADESTO TECHNOLOGY CORPORATION
Reel/Frame 024953/0554 →
CONTRIBUTION AGREEMENT (RELEVANT PARTS; ENGLISH TRANSLATION) Recorded Oct 6, 2009
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023330/0771 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2006
From: UFERT, KLAUS- DIETER
To: INFINEON TECHNOLOGIES AG
Reel/Frame 017473/0159 →