Channel discharging after erasing flash memory devices
View Patent ↗A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate but not allowed into a deeper well of opposite conductivity type relative to the upper well. After a brief time, T, the charged particles are pushed by a bias voltage into the deeper well from the upper well. This two step clearing procedure avoids device latchup that might occur otherwise.
1. A method of channel clearing in a double well floating gate non-volatile memory device subject to sequential program and erase operations comprising:
discharging the floating gate into a double well vertical p and n type subsurface structure, said structure being disposed in a substrate of the non-volatile memory device and being insulated from the floating gate of the device, by applying an erase voltage at a first causing charged particle flow from the floating gate to a first well in the substrate;
then at a second time discharging the first well into a second well in the substrate by using a switch applying a channel-clearing voltage causing charged particle flow from the first well into the second well; and
then at a third time discharging the second well using said switch.
2. The method of claim 1 wherein the erase voltage is a greater potential than the channel-clearing voltage.
3. The method of claim 1 wherein the discharging of the second well is applied at a time, T, after the discharging of the first well wherein the time, T, is less than the time for a next sequential program and erase operation.
4. A method of channel clearing in a double well floating gate non-volatile memory device subject to sequential program and erase operations comprising:
discharging the floating gate at a first time by controlling voltages on a control gate above the floating gate and in a subsurface region below the floating gate; and
starting a channel clearing operation at a second time after initiation of the discharging step at a first voltage level but changing to a second voltage level at a third time before the next memory operation that provides a discharge path through the double wells.
5. The method of claim 4 wherein voltages in the subsurface region below the floating gate is applied through double wells, one double well atop the other double well.
6. The method of claim 4 wherein the first voltage level establishes a greater potential difference relative to the voltage in a control gate above the floating gate than the second voltage level.
7. The method of claim 5 wherein said double wells form a parasitic p-n diode junction wherein said first and second voltage levels provide a reverse bias across the p-n junction.
8. A method of channel clearing in a double well floating gate memory transistor having a control gate above the floating gate and a substrate of a first conductivity type, a first well of the first conductivity type in a deep second well of a second conductivity type thereby forming at least one subsurface parasitic p-n junction, comprising:
discharging the floating gate at a first time by a high voltage having a first polarity on the control gate and a second polarity on both the first well and the second well;
clearing the channel at a second time later than the first time by grounding the control gate and grounding the first well while allowing the second well to remain at the voltage of the second polarity thereby reverse biasing the parasitic p-n junction of first and second wells;
after a third time, lowering the voltage of the second well to an intermediate voltage while the first well remains at ground.
9. The method of claim 8 wherein the voltage of the first polarity for discharging the floating gate is approximately equal in voltage to the voltage of second polarity.