Resistive memory arrangement
View Patent ↗Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.
1. A resistive memory arrangement having a cell array structured in rows and columns, comprising:
resistive memory cells connected to a drive element for driving;
each drive element jointly being connected to n cell resistors forming a memory cell;
wherein control electrodes of the drive elements of a column are jointly connected to a word line running in the column direction;
wherein first controlled electrodes of the drive elements of a row are jointly connected to a bit line running in the row direction;
wherein second controlled electrodes of each drive element are in each case connected to the first electrodes of the n cell resistors; and
wherein the second electrodes of the n cell resistors of each column are individually connected in each case to a plate line running in the column direction.
2. The memory of claim 1 , wherein the drive elements are FET transistors.
3. The memory arrangement of claim 1 , wherein the cell resistors are CBRAM resistance elements.
4. The memory arrangement of claim 3 , wherein the anodes of the CBRAM resistance elements are connected to the plate lines and the cathodes of the CBRAM resistance elements are connected to the drive element.
5. The memory arrangement of claim 4 , wherein a diode is in each case connected in the forward direction or in the breakdown direction in series with the CBRAM resistance elements.
6. The memory arrangement of claim 3 , wherein a selected CBRAM resistance element of the memory cells is programmed to a suitable resistance value having a lower resistance than the resistance values of the other CBRAM resistance elements in the same memory cell.
7. The memory arrangement of claim 1 , wherein each memory cell contains n=4 cell resistors.
8. A memory comprising:
a drive element having a control terminal, a first controlled terminal and a second controlled terminal;
a word line running in the column direction coupled to the control terminal of the drive element;
a bit line running in the row direction coupled to the first controlled electrode of the drive element; and
a plurality of cell resistors each having first and second terminals;
wherein the second controlled terminal of the drive element is coupled to the first terminal of each of the plurality of cell resistors; and
wherein the second terminal of each of the plurality of the cell resistors are individually coupled a plate line running in the column direction.
9. The memory of claim 8 , wherein jointly connecting the drive element to the plurality of cell resistors forms a memory cell.
10. The memory of claim 8 , wherein the drive elements are FET transistors.
11. The memory of claim 9 , wherein the cell resistors are CBRAM resistance elements.
12. The memory of claim 11 , wherein the anodes of the CBRAM resistance elements are connected to the plate lines and the cathodes of the CBRAM resistance elements are connected to the drive element.
13. The memory of claim 12 , wherein a diode is in each case connected in the forward direction or in the breakdown direction in series with the CBRAM resistance elements.
14. The memory of claim 11 , wherein a selected CBRAM resistance element of the memory cell is programmed to a suitable resistance value having a lower resistance than the resistance values of the other CBRAM resistance elements in the same memory cell.
15. The memory arrangement of claim 9 , wherein each memory cell contains 4 cell resistors.
16. A memory comprising:
a drive element having a control terminal, a first controlled terminal and a second controlled terminal;
a word line coupled to the control terminal of the drive element;
a bit line coupled to the first controlled electrode of the drive element; and
a plurality of CBRAM resistance elements coupled to the second controlled terminal of the drive element.
17. The memory of claim 16 further comprising a plate line, wherein the plurality of CBRAM resistance elements are coupled between the plate line and the second controlled terminal of the drive element.
18. The memory of claim 16 , wherein the drive elements are FET transistors.
19. The memory of claim 16 , wherein connecting the drive element to the plurality of CBRAM resistance elements forms a memory cell.
20. The memory arrangement of claim 19 , wherein each memory cell contains 4 CBRAM resistance elements.