IP Library Granted Patent US 7,658,773
Granted Patent B2
US 7,658,773 · App. 11/541,391 · Granted Feb 9, 2010

Method for fabricating a solid electrolyte memory device and solid electrolyte memory device

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Quick Facts
Patent No.
US 7,658,773
App. No.
11/541,391
Granted
Feb 9, 2010
Kind
B2
Abstract

A method for fabricating a solid electrolyte memory device comprises a plurality of solid electrolyte memory cells, the solid electrolyte memory cells sharing a common continuous solid electrolyte layer comprising solid electrolyte cell areas and solid electrolyte inter-cell areas, the method comprising the process of introducing mobile ion solubility reducing material or mobile ion mobility reducing material into the solid electrolyte inter-cell areas.

Claims (31)

1. A method of fabricating a solid electrolyte memory device comprising a plurality of solid electrolyte memory cells, the method comprising:

providing a composite structure, the composite structure including a first electrode layer, a second electrode layer and a continuous solid electrolyte layer between the first electrode layer and the second electrode layer;

the first electrode layer comprising at least one first electrode,

the second electrode layer comprising a plurality of second electrodes, and

the continuous solid electrolyte layer comprising solid electrolyte cell areas and solid electrolyte inter-cell areas, each of the solid-electrolyte cell areas being located between a first electrode and a second electrode, and the solid electrolyte inter-cell areas being located between the solid electrolyte cell areas; and

introducing mobile ion solubility reducing material or mobile ion mobility reducing material into the solid electrolyte inter-cell areas.

2. The method according to claim 1 , wherein the introducing of mobile ion solubility reducing material or mobile ion mobility reducing material into the continuous solid electrolyte layer comprises an ion implantation process.

3. The method according to claim 2 , wherein the ion implantation process is performed using implantation energies lower than 10 keV.

4. The method according to claim 2 , wherein the ion implantation process is performed at room temperature.

5. The method according to claim 2 , wherein the ion implantation process is performed using an implantation mask covering the solid electrolyte cell areas.

6. The method according to claim 2 , wherein the solid electrolyte layer is subjected to a heat treating process after the ion implantation process.

7. The method according to claim 1 , wherein the introducing of mobile ion solubility reducing material or mobile ion mobility reducing material into the solid electrolyte inter-cell areas comprise a diffusion process.

8. The method according to claim 7 , wherein the diffusion process comprises subjecting at least one layer which is disposed adjacent to the solid electrolyte layer and which comprises mobile ion solubility reducing material or mobile ion mobility reducing material to an annealing process.

9. The method according to claim 8 , wherein the at least one layer comprising mobile ion solubility reducing material or mobile ion mobility reducing material comprises a silicon nitride (SiN) layer located within the second electrode layer within regions which face solid electrolyte inter-cell areas.

10. The method according to claim 1 , wherein the introducing of mobile ion solubility reducing material or mobile ion mobility reducing material into the solid electrolyte inter-cell areas comprise a plasma treatment process.

11. The method according to claim 10 , wherein the plasma treatment process comprises exposing the solid electrolyte inter-cell areas to a plasma.

12. The method according to claim 10 , further comprising covering the solid electrolyte cell areas with a protection film before the exposing the solid electrolyte inter-cell areas to the plasma.

13. The method according to claim 10 , wherein the plasma comprises a main gas comprising at least one of the elements argon (Ar), helium (He), krypton (Kr), neon (Ne) and xenon (Xe), and a compound gas comprising at least one of the gaseous compounds O 2 , O 3 , H 2 O, NO, NO 2 , SO 2 , SO, CO, and CO 2 .

14. The method according to claim 1 , wherein the solid electrolyte layer comprises chalcogenide.

15. The method according to claim 1 , wherein the mobile ion solubility reducing material or mobile ion mobility reducing material comprises oxygen.

16. The method according to claim 1 , wherein the mobile ions comprise silver (Ag) ions.

17. The method according to claim 1 , wherein an amount of the mobile ion solubility reducing material or mobile ion mobility reducing material is chosen such that a concentration of the mobile ion solubility reducing material or mobile ion mobility reducing material within the solid electrolyte inter-cell areas is at least about 1 ppm.

18. The method according to claim 1 , wherein an amount of the mobile ion solubility reducing material or mobile ion mobility reducing material is chosen such that a concentration of the mobile ion solubility reducing material or mobile ion mobility reducing material within the solid electrolyte inter-cell areas is more than about 1 at %.

19. The method according to claim 1 , further comprising introducing metallic material into the solid electrolyte cell areas.

20. The method according to claim 19 , wherein introducing metallic material into the solid electrolyte cell areas comprises using ion implantation process.

21. The method according to claim 20 , wherein the using an ion implantation process comprises using an implantation mask covering the continuous solid electrolyte layer such that the solid electrolyte cell areas of the solid electrolyte layer are exposed.

22. The method according to claim 19 , wherein the introducing metallic material into the solid electrolyte cell areas comprises using a diffusion process.

23. The method according to claim 19 , wherein the introducing metallic material into the solid electrolyte cell areas comprises using a plasma treatment process.

24. The method according to claim 1 , wherein the first electrode layer is a top electrode layer, and the second electrode layer is a bottom electrode layer.

25. The method according to claim 1 , wherein the first electrode layer comprises a single continuous first electrode.

26. A method of fabricating a solid electrolyte memory device comprising a plurality of solid electrolyte memory cells, the solid electrolyte memory cells sharing a common continuous solid electrolyte layer comprising solid electrolyte cell areas and solid electrolyte inter-cell areas, the method comprising introducing mobile ion solubility reducing material or mobile ion mobility reducing material into the solid electrolyte inter-cell areas.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Sep 24, 2019
From: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 050480/0836 →
RELEASE OF SECURITY INTEREST Recorded May 9, 2019
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 049125/0970 →
SECURITY INTEREST Recorded May 8, 2018
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
Reel/Frame 046105/0731 →
RELEASE OF SECURITY INTEREST Recorded Oct 3, 2017
From: WESTERN ALLIANCE BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 044219/0610 →
SECURITY INTEREST Recorded May 22, 2015
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 035754/0580 →
RELEASE OF SECURITY INTEREST Recorded Oct 15, 2013
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 031414/0232 →
SECURITY AGREEMENT Recorded Oct 7, 2013
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: BRIDGE BANK, NATIONAL ASSOCIATION
Reel/Frame 031371/0581 →
SECURITY AGREEMENT Recorded Oct 8, 2012
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 029090/0922 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEES ERRONEOUSLY NAMED AS INFINEON TECHNOLOGIES AG AND ALTIS SEMICONDUCTOR PREVIOUSLY RECORDED ON REEL 018669 FRAME 0344. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT ASSIGNEES TO BE QIMONDA AG AND ALTIS SEMICONDUCTOR. Recorded Nov 5, 2010
From: PINNOW, CAY-UWE
To: QIMONDA AG; ALTIS SEMICONDUCTOR
Reel/Frame 025317/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2010
From: QIMONDA AG
To: ADESTO TECHNOLOGY CORPORATION
Reel/Frame 024953/0554 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2010
From: PINNOW, CAY-UWE
To: ALTIS SEMICONDUCTOR; INFINEON TECHNOLOGIES AG
Reel/Frame 024953/0550 →
CONTRIBUTION AGREEMENT (RELEVANT PARTS; ENGLISH TRANSLATION) Recorded Oct 6, 2009
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023330/0771 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2006
From: PINNOW, CAY-UWE
To: INFINEON TECHNOLOGIES AG; ALTIS SEMICONDUCTOR
Reel/Frame 018669/0344 →