IP Library Granted Patent US 8,369,132
Granted Patent B1
US 8,369,132 · App. 13/337,004 · Granted Feb 5, 2013

Methods of programming and erasing programmable metallization cells (PMCs)

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Quick Facts
Patent No.
US 8,369,132
App. No.
13/337,004
Granted
Feb 5, 2013
Kind
B1
Abstract

A method can include programming a selected programmable metallization cell (PMC) by coupling the anodes of a group of PMCs to a first power supply voltage and connecting a cathode of one of PMCs of the group to a second power supply voltage with a select device; and erasing a selected PMC by coupling the anodes of a group of PMCs to the second power supply voltage and connecting the cathode of one of PMCs of the group to the first supply voltage with the select device.

Claims (54)

1. A method, comprising the steps of:

programming a selected programmable metallization cell (PMC) by coupling the anodes of a group of PMCs to a first power supply voltage and connecting a cathode of one of PMCs of the group to a second power supply voltage with a select device; and

erasing a selected PMC by coupling the anodes of a group of PMCs to the second power supply voltage and connecting the cathode of one of PMCs of the group to the first supply voltage with the select device.

2. The method of claim 1 , wherein:

the anodes of the PMCs of the group are commonly connected to a bit line;

programming the selected PMC includes coupling the bit line a write circuit via a bit line multiplexer (MUX); and

erasing the selected PMC include coupling the bit line to the write circuit via the bit line MUX; wherein

the write circuit receives the first and second power supply voltages.

3. The method of claim 1 , wherein:

the cathodes of the PMCs of the group are commonly connected to a source strap by corresponding select devices;

programming the selected PMC includes coupling the source strap to the second power supply voltage with a source select circuit; and

erasing the selected PMC include coupling the source strap to the first power supply voltage with the source select circuit.

4. The method of claim 1 , wherein:

the anodes of the PMCs of the group are commonly connected to a bit line;

the bit line is coupled to a bit line selection circuit;

programming the selected PMC includes driving the bit line to the first power supply voltage with bit line selection circuit; and

erasing the selected PMC includes driving the bit line to the second power supply voltage with the bit line selection circuit.

5. The method of claim 4 , wherein:

programming the selected PMC includes enabling a p-channel transistor in the a bit line selection circuit that is coupled between the first power supply voltage and the bit line; and

erasing the selected PMC includes enabling an n-channel transistor in the a bit line selection circuit that is coupled between the second power supply voltage and the bit line.

6. The method of claim 1 , further including:

reading a selected PMC by coupling the anodes of a group of PMCs to a read voltage and connecting the cathode of one of PMCs of the group of to the second power supply voltage with the select device.

7. The method of claim 6 , wherein:

the anodes of the PMCs of the group are commonly connected to a bit line; and

reading the selected PMC includes coupling the bit line to the read voltage with a bit line multiplexer (MUX).

8. The method of claim 6 , wherein:

the cathodes of the PMCs of the group are commonly connected to a source strap by corresponding select devices; and

reading the selected PMC includes coupling the bit line to the second power supply voltage.

9. The method of claim 1 , further including:

de-selecting a PMC from programming or erasing by electrically isolating the anodes of the group of PMCs that includes the de-selected PMC, and electrically isolating the select device coupled to the de-selected PMC.

10. The method of claim 9 , wherein:

the anodes of the PMCs of the group are commonly connected to a bit line;

the bit line is coupled to a bit line selection circuit; and

de-selecting the PMC includes

disabling a p-channel transistor in the a bit line selection circuit to isolate the bit line from the first power supply voltage, and

disabling an n-channel transistor in the a bit line selection circuit to isolate the bit line from the second power supply voltage.

11. The method of claim 1 , further including:

de-selecting a PMC by coupling the anodes of the group of PMCs to a de-select potential, and coupling the select device coupled to the de-selected PMC to a de-select potential.

12. The method of claim 11 , wherein:

the de-select potential is the second power supply voltage.

13. The method of claim 11 , wherein:

the de-select potential is between the first power supply voltage and the second power supply voltage.

14. The method of claim 1 , wherein:

the cathodes of the PMCs of the group are commonly connected to a source strap by corresponding select devices; and

programming the selected PMC includes disabling the select devices corresponding to the non-selected PMCs of the group.

15. The method of claim 1 , wherein:

the cathodes of the PMCs of the group are commonly connected to a source strap by corresponding select devices; and

erasing the selected PMC includes disabling the select devices corresponding to the non-selected PMCs of the group.

16. The method of claim 1 , wherein:

the cathodes of the PMCs of the group are commonly connected to a source strap by corresponding select devices, each select device is coupled to a different word line; and

programming the selected PMC includes activating one word line while de-activating the other word lines.

17. The method of claim 1 , wherein:

the cathodes of the PMCs of the group are commonly connected to a source strap by corresponding select devices, each select device is coupled to a different word line; and

erasing the selected PMC includes activating one word line while de-activating the other word lines.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2023
From: RENESAS DESIGN US INC. (FORMERLY KNOWN AS DIALOG SEMICONDUCTOR US INC. AS SUCCESSOR-IN-INTEREST TO ADESTO TECHNOLOGIES CORPORATION AND ARTEMIS ACQUISITION, LLC)
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 063118/0352 →
RELEASE OF SECURITY INTEREST Recorded Sep 24, 2019
From: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 050480/0836 →
RELEASE OF SECURITY INTEREST Recorded May 9, 2019
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 049125/0970 →
SECURITY INTEREST Recorded May 8, 2018
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
Reel/Frame 046105/0731 →
RELEASE OF SECURITY INTEREST Recorded Oct 3, 2017
From: WESTERN ALLIANCE BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 044219/0610 →
SECURITY INTEREST Recorded May 22, 2015
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 035754/0580 →
RELEASE OF SECURITY INTEREST Recorded Oct 15, 2013
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 031414/0232 →
SECURITY AGREEMENT Recorded Oct 7, 2013
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: BRIDGE BANK, NATIONAL ASSOCIATION
Reel/Frame 031371/0581 →
SECURITY AGREEMENT Recorded Oct 8, 2012
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 029090/0922 →