CBRAM/ReRAM with improved program and erase algorithms
View Patent ↗Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of controlling a programmable impedance element can include: (i) receiving a program or erase command to be executed on the programmable impedance element; (ii) selecting an operation algorithm for executing the command, where the operation algorithm is selected from among a plurality of operation algorithms by decoding at least two bits stored in a register; (iii) determining, using the register, a plurality of option variables for the selected operation algorithm, where the option variables are used to set conditions for one or more of a plurality of program and erase operations of the selected operation algorithm; and (iv) executing the command on the programmable impedance element by performing the one or more of the plurality of program and erase operations of the selected operation algorithm.
1. A method of controlling a programmable impedance element, the method comprising:
a) receiving a program or erase command to be executed on the programmable impedance element;
b) selecting an operation algorithm for executing the command, wherein the operation algorithm is selected from among a plurality of operation algorithms by decoding at least two bits stored in a register;
c) determining, using the register, a plurality of option variables for the selected operation algorithm, wherein the option variables are used to set conditions for one or more of a plurality of program and erase operations of the selected operation algorithm; and
d) executing the command on the programmable impedance element by performing the one or more of the plurality of program and erase operations of the selected operation algorithm.
2. The method of claim 1 , wherein the plurality of option variables comprises option variables for pulse widths, voltages, and currents.
3. The method of claim 1 , wherein the plurality of option variables comprises a number of retry loops.
4. The method of claim 1 , wherein the command comprises a program command.
5. The method of claim 4 , wherein the selected operation algorithm for the program command comprises programming with a first condition.
6. The method of claim 5 , wherein the selected operation algorithm for the program command comprises programming with a third condition if the programming with the first condition results in a failure to program the programmable impedance element.
7. The method of claim 6 , wherein the selected operation algorithm for the program command comprises:
a) setting a status flag to fail if the programming with the third condition results in a failure to program the programmable impedance element; and
b) setting a status flag to pass if either of the programming with the first or third conditions results in successful programming of the programmable impedance element.
8. The method of claim 4 , wherein the selected operation algorithm for the program command comprises:
a) initializing a retry counter;
b) programming with a first condition; and
c) setting a status flag to pass if the programming with the first condition results in successful programming of the programmable impedance element.
9. The method of claim 8 , wherein if the programming with the first condition results in a failure to program the programmable impedance element, the selected operation algorithm for the program command comprises:
a) erasing with a first condition;
b) programming with a second condition; and
c) setting a status flag to pass if the programming with the second condition results in successful programming of the programmable impedance element.
10. The method of claim 9 , wherein if the programming with the second condition results in a failure to program the programmable impedance element, the selected operation algorithm for the program command comprises:
a) incrementing the retry counter; and
b) returning to the erasing with the first condition if the retry counter is less than or equal to a predetermined maximum.
11. The method of claim 9 , wherein if the programming with the second condition results in a failure to program the programmable impedance element, the selected operation algorithm for the program command comprises:
a) programming with a third condition;
b) setting a status flag to pass if the programming with the third condition results in successful programming of the programmable impedance element.
12. The method of claim 11 , wherein if the programming with the third condition results in a failure to program the programmable impedance element, the selected operation algorithm for the program command comprises:
a) incrementing the retry counter; and
b) returning to the erasing with the first condition if the retry counter is less than or equal to a predetermined maximum.
13. The method of claim 1 , wherein the command comprises an erase command.
14. The method of claim 1 , further comprising:
a) reading data from a designated register data portion of a memory array, wherein the memory array comprises the programmable impedance element; and
b) programming the register with the data read from the designated register data portion.
15. The method of claim 14 , wherein the memory array comprises a plurality of memory cells, wherein each of the memory cells comprises:
a) a programmable impedance element having an active electrode coupled to a bit line; and
b) a transistor having a drain coupled to the inert electrode of the programmable impedance element, a gate coupled to a word line, and a source coupled to a source line.
16. The method of claim 1 , wherein the programmable impedance element comprises:
a) an inert electrode coupled to a first side of a solid electrolyte;
b) an active electrode coupled to a second side of the solid electrolyte, wherein the programmable impedance element is programmed by formation of a conductive path between the active and inert electrodes; and
c) a plurality of mobile elements derived from the active electrode, wherein the plurality of mobile elements are reduced in the solid electrolyte to form the conductive path.
17. The method of claim 16 , wherein the conductive path in the programmable impedance element is formed by application of a first voltage across the active and inert electrodes, the conductive path remaining once formed after the first voltage is removed.
18. The method of claim 16 , wherein at least a portion of the conductive path is dissolved to erase the programmable impedance element by application of a second voltage across the active and inert electrodes.
19. The method of claim 1 , further comprising overriding the data in the register during a test mode.
20. An apparatus for controlling a programmable impedance element, the apparatus comprising:
a) means for receiving a program or erase command to be executed on the programmable impedance element;
b) means for selecting an operation algorithm for executing the command, wherein the operation algorithm is selected from among a plurality of operation algorithms by decoding at least two bits stored in a register;
c) means for determining, using the register, a plurality of option variables for the selected operation algorithm, wherein the option variables are used to set conditions for one or more of a plurality of program and erase operations of the selected operation algorithm; and
d) means for executing the command on the programmable impedance element by performing the one or more of the plurality of program and erase operations of the selected operation algorithm.