Granted Patent B2

US 7,551,498 · App. 11/611,452 · Granted Jun 23, 2009

Abstract

Claims (88)

1. A memory having column redundancy, comprising:

a regular memory array having regular column decoders and regular senses;

a redundant memory array having a redundant column decoder and redundant senses;

redundant latches that are coupled to one of the redundant senses, wherein the redundant latches include cross-coupled inverter circuits each configured to receive an activation signal operable to activate a selected latch and to receive an enabling signal operable to enable the selected latch, and to generate an output operable to activate a corresponding redundant sense;

redundancy comparison logic that compares an address of a defective regular memory cell with input addresses to disable the regular senses for a defective regular memory and to enable a corresponding redundant latch that is coupled to one of the redundant senses to activate a redundant column in the redundant memory array.

2. A column redundancy system for a flash memory, comprising:

a redundant memory array having r columns of redundant memory cells:

r redundant senses:

a redundant column decoder coupled between the redundant memory array and the r redundant senses:

redundant address registers that store addresses of defective regular memory cells;

n groups of r redundant latches, where each of the r redundant latches from a group is coupled to a respective one of the redundant column senses, wherein each of the redundant latches includes a latch circuit that has a latch input terminal and a latch output terminal and that includes a pair of cross-coupled inverters that have an input terminal of one coupled to an output terminal of the other;

redundancy comparison logic that compares addresses of defective regular memory cells stored in the redundant address registers with an external input address and, if the comparison is true, that provide a DISABLE LOAD signal to disable the regular senses for one of the n groups of m columns, that provides an ENABLE LATCH signal to one of the n groups of r latches to enable corresponding redundant latches, and that provides one of r REDO signals to a respective one of the r redundant latches in one of the one of the n groups that is disabled; and

wherein the selected one of the redundant latches activates one of the r redundant senses.

3. The column redundancy system of claim 2 wherein the redundant senses are activated by being pulled down by one of the redundant latches.

4. The column redundancy system of claim 3 wherein the n×r redundant latches are open drain circuits that allow n redundant latches on each of the r redundant senses.

5. The column redundancy system of claim 2 wherein each of the redundant latches includes an input circuit that requires both an ENABLE_LATCH signal and one of the REDO signals to activate a redundant latch.

6. The column redundancy system of claim 5 wherein the input circuit for each of the redundant latches includes two series coupled transistors, one of which is turned on by an ENABLE_LATCH signal and the other of which is turned on by a REDO signal.

7. The column redundancy system of claim 6 wherein each of the redundant latches includes an NMOS output transistor that has a gate terminal coupled to the output terminal of the latch, that has a source coupled to a ground terminal, and that has an open drain that is coupled to one of the r redundant senses.

8. The column redundancy system of claim 2 wherein the memory enable signal that provides the LOAD_PL signal to the n×m regular senses to initiate operation of the regular senses is a write enable (WE) signal for the flash memory.

9. A flash memory having column redundancy, the flash memory comprising:

a regular memory array having n×m columns of regular memory cells collected in n groups of m columns;

n×m regular senses having n I/O terminals;

a command user interface that receives a memory enable signal to provide a LOAD_PL signal to the n×m regular senses to initiate operation of the regular senses;

means for disabling the n×m regular senses;

a column decoder coupled between the regular memory array and the regular senses;

a redundant memory array having r columns of redundant memory cells;

r redundant senses in electrical communication with the regular senses;

a redundant column decoder coupled between the redundant memory array and the r redundant senses;

redundant address registers that store addresses of defective regular memory cells;

r redundant latches in n groups of redundant latches, where each of the r redundant latches from a group is coupled to a respective one of the redundant senses, and wherein each of the redundant latches includes a latch circuit that has a latch input terminal and a latch output terminal and that includes a pair of cross-coupled inverters that have an input terminal of one coupled to an output terminal of the other;

redundancy comparison logic that compares addresses of defective regular memory cells stored in the redundant address registers with an external input address and, if the comparison is true, that provide a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, that provides an ENABLE_LATCH signal to one of the n groups of r latches to enable corresponding redundant latches, and that provides one of r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled; and

wherein the selected one of the redundant latches activates one of the r redundant senses to activate one of the redundant columns.

10. The flash memory of claim 9 comprising means for activating the redundant senses by being pulled down by one of the redundant latches.

11. The flash memory of claim 10 wherein then n×r redundant latches are open drain circuits that allow n redundant latches to be coupled with each of the r redundant senses.

12. The flash memory of claim 9 wherein each of the redundant latches includes an input circuit that requires both an ENABLE_LATCH signal and one of the REDO signals to activate a redundant latch.

13. The flash memory of claim 12 wherein the input circuit for each of the redundant latches includes two series coupled transistors, one of which is turned on by an ENABLE_LATCH signal and the other of which is turned on by a REDO signal.

14. The flash memory of claim 13 wherein each of the redundant latches includes an NMOS output transistor that has a gate terminal coupled to the output terminal of the latch, that has a source coupled to a ground terminal, and that has an open drain that is coupled to one of the r redundant senses.

15. The flash memory of claim 9 wherein the memory enable signal that provides the LOAD_PL signal to the n×m regular senses to initiate operation of the regular senses is a write enable (WE) signal for the flash memory.

16. A method of providing column redundancy for a memory, comprising:

coupling a redundant column decoder between a redundant memory array and a redundant column sense;

coupling a group of redundant latches to a respective redundant colunm sense wherein the redundant latches include cross-coupled inverter circuits each configured to receive an activation signal operable to activate a selected latch and to receive an enabling signal operable to enable the selected latch;

comparing an address of a defective regular memory cell with external input addresses;

disabling regular senses; and

enabling a redundant latch in response to an output of a corresponding cross-coupled inverter circuit to activate a redundant sense for the redundant memory array.

17. The method of claim 16 including activating the redundant sense by pulling it down by a selected one of the redundant latches.

18. The method of claim 17 including selecting one of a group of redundant latches.

19. A column redundancy system for a flash memory, comprising:

a redundant memory array having r columns of redundant memory cells;

r redundant senses;

a redundant column decoder coupled between the redundant memory array and the r redundant senses;

redundant address registers that store addresses of defective regular memory cells;

n groups of r redundant latches, where at least one of the r redundant latches from a group is coupled to a respective one of the redundant colunm senses;

redundancy comparison logic that compares addresses of defective regular memory cells stored in the redundant address registers with an external input address and, if the comparison is true, that provide a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, that provides an ENABLE_LATCH signal to one of the n groups of r latches to enable corresponding redundant latches, and that provides one of r REDO signals to a respective one of the r redundant latches in one of the one of the n groups that is disabled, wherein at least one of the redundant latches includes an input circuit that requires both an ENABLE_LATCH signal and one of the REDO signals to activate a redundant latch; and

wherein the selected one of the redundant latches activates one of the r redundant senses.

20. The column redundancy system of claim 19 , wherein the redundant senses are activated by being pulled down by one of the redundant latches.

21. The column redundancy system of claim 20 , wherein the n×r redundant latches are open drain circuits that allow n redundant latches on each of the r redundant senses.

22. The column redundancy system of claim 19 , wherein the input circuit for each of the redundant latches includes two series coupled transistors, one of which is turned on by an ENABLE_LATCH signal and the other of which is turned on by a REDO signal.

23. The column redundancy system of claim 22 , wherein each of the redundant latches includes an NMOS output transistor that has a gate terminal coupled to the output terminal of the latch, that has a source coupled to a ground terminal, and that has an open drain that is coupled to one of the r redundant senses.

24. The flash memory of claim 23 wherein at least of the redundant latches includes an NMOS output transistor that has a gate terminal coupled to the output terminal of the latch, that has a source coupled to a ground terminal, and that has an open drain that is coupled to one of the r redundant senses.

25. The flash memory of claim 22 , wherein the input circuit for at least one of the redundant latches includes two series coupled transistors, one of which is turned on by an ENABLE_LATCH signal and the other of which is turned on by a REDO signal.

26. The memory of claim 25 wherein a plurality of redundant latches are coupled to a redundant sense and the redundant sense is activated by one of the redundant latches.

27. The memory of claim 25 wherein the redundant latches are open drain circuits that allow a number of redundant latches to be coupled to a redundant sense.

28. A flash memory having column redundancy, the flash memory comprising:

a regular memory array having n×m columns of regniar memory cells collected in n groups of m columns;

n×m regnlar senses having n I/O terminals;

a command user interface that receives a memory enable signal to provide a LOAD_PL signal to the n×m regular senses to initiate operation of the regular senses;

a disabling circuit to disable the n×m regular senses;

a column decoder coupled between the regular memory array and the regular senses;

a redundant memory array having r columns of redundant memory cells;

r redundant senses in electrical communication with the regular senses;

a redundant column decoder coupled between the redundant memory array and the r redundant senses;

redundant address registers that store addresses of defective regular memory cells;

r redundant latches in n groups of redundant latches, where each of the r redundant latches ftom a group is coupled to a respective one of the redundant senses;

redundancy comparison logic that compares addresses of defective regular memory cells stored in the redundant address registers with an external input address and, if the comparison is true, that provide a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, that provides an ENABLE_LATCH signal to one of the n groups of r latches to enable corresponding redundant latches, and that provides one of r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled, wherein each of the redundant latches includes an input circuit that requires both an ENABLE_LATCH signal and one of the REDO signals to activate the redundant latch; and

wherein the selected one of the redundant latches activates one of the r redundant senses to activate one of the redundant columns.

29. A flash memory having column redundancy, the flash memory comprising:

a regular memory array having n×m columns of regular memory cells collected in n groups of m columns;

n×m regular senses having n I/O terminals;

a command user interface that receives a memory enable signal to provide a LOAD_PL signal to the n×m regular senses to initiate operation of the regular senses, wherein the memory enable signal that provides the LOAD_PL signal includes a write enable (WE) signal;

a disabling device to disable the n×m regular senses;

a colunm decoder coupled between the regular memory array and the regular senses;

a redundant memory array having r columns of redundant memory cells;

r redundant senses in electrical communication with the regular senses;

a redundant column decoder coupled between the redundant memory array and the r redundant senses;

redundant address registers that store addresses of defective regular memory cells;

r redundant latches in n groups of redundant latches, wherein the r redundant latches from a group is coupled to a respective one of the redundant senses;

redundancy comparison logic that compares addresses of defective regular memory cells stored in the redundant address registers with an external input address and, if the comparison is true, that provide a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, that provides an ENABLE_LATCH signal to one of the n groups of r latches to enable corresponding redundant latches, and that provides one of r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled; and

wherein the selected one of the redundant latches activates one of the r redundant senses to activate one of the redundant columns.

Assignments (9)