Memory devices, architectures and methods for memory elements having dynamic change in property

1. A memory device, comprising:

at least one array comprising a plurality of elements programmable between at least two different states, each state having a different time to a change in property under applied sense conditions;

a read circuit configured to apply the sense conditions to selected elements and detect changes in property in the selected elements to generate read data;

a latch circuit configured to store read data from the read circuit; and

a transfer path configured to provide a parallel data transfer path between the read circuit and the latch circuit.

2. The memory device of 1 , further including:

the read circuit is configured to access at least N bits of data in parallel;

the transfer path is configured to transfer N bits of data in parallel between the read circuit and the latch circuit; and

an input/output (I/O) circuit configured to transfer data between the latch circuit and a data I/O path in groups of P bits, where P<N.

3. The memory device of claim 1 , further including:

a first decoding circuit coupled to the array and configured to connect a group of elements to the read circuit in response to at least a first portion of an address value; and

a second decoding circuit configured to couple a portion of the data storage locations in the latch circuit to an external data path in response to at least a second portion of the address value.

4. The memory device of claim 1 , further including:

a serial input/output (I/O) circuit configured to selectively transfer data between the latch circuit and a serial connection in at least one serial data stream.

5. The memory device of claim 1 , wherein:

each element comprises at least one ion conducting layer formed between two electrodes.

6. The memory device of claim 1 , wherein:

the transfer path transfers no less than 128 bits in parallel between the read circuit and the latch circuit.

7. The memory device of claim 1 , wherein:

the plurality of elements includes first elements;

the read circuit includes

at least one sense amplifier configured to compare electrical signals received at two inputs to generate a sense data value;

at least one reference circuit configured to generate a reference signal different from those generated by the first elements; and

a reference switching circuit configured to couple one first element to one input of the sense amplifier and couple the reference circuit to another input of the sense amplifier.

8. The memory device of claim 1 , wherein:

the at least two different states of the memory elements include

a first state in which an element undergoes a change in property within a time t1, and

a second state in which an element does not undergo the change in property within the time t1.

9. The memory device of claim 7 , wherein:

the reference circuit comprises at least one reference element programmable to a reference state in which the reference element undergoes a change in property different from that of the first elements under the sense conditions.

10. The memory device of claim 9 , further including:

the reference circuit further includes a second reference element programmable to the reference state; and

a conditioning circuit that selectively applies conditioning electrical signals to the second reference element, while the first reference element is connected to the at least one sense amplifier, the conditioning electrical signals substantially reversing property changes caused by applying sense conditions to the second reference element.

11. The memory device of claim 9 , further including:

a plurality of second memory elements programmable between at least the two different states;

the reference circuit further includes a second reference element programmable to the reference state; and

the reference switching circuit is further configured to couple one second memory element to one input of the sense amplifier and couple the second reference circuit to another input of the sense amplifier.

12. The memory device of claim 9 , further including:

the at least one array includes a first bit line and a second bit line;

each first element is coupled to the first bit line by a first access device, each first access device being selectively enabled by a select signal on a corresponding first word line; and

the reference switching circuit includes at least a first reference element coupled to the second bit line by a reference access device enabled by a first reference enable signal; wherein

the first reference element is programmable to a reference state in which the reference element undergoes a change in property different from that of the first elements under the sense conditions.

13. The memory device of claim 12 , further including:

the plurality of elements includes second elements, each second element being coupled to the second bit line by a second access device, each access device being selectively enabled by a select signal on a corresponding first word line; and

the second bit line has a location selected from the group of: a same physical side of the sense amplifier as the first bit line, and a physical side of the sense amplifier opposite to that of the first bit line.

14. The memory device of claim 7 , wherein:

at least one sense amplifier comprises a latch formed by drivers cross coupled between first and second latching nodes; and

the reference switching circuit includes a data switch path configured to couple first elements to the first latching node and a reference switch path configured to couple the reference circuit to the second latching node.

15. The memory device of claim 7 , further including:

precharge circuits, coupled to first and second bit lines, and configured to precharge the first and second bit lines to a precharge voltage prior to the sense amplifier generating the sense data value.

16. The memory device of claim 1 , wherein:

each first element includes a memory material formed between a first electrode a second electrode, each first electrode being coupled to a first bit line, each second electrode being coupled to a conductive plate structure; and

a plate driving circuit that drives the plate structure to a read drive voltage in a read operation.

17. The memory device of claim 16 , further including:

precharge circuits, coupled to at least the first bit lines and configured to precharge the first bit lines to a precharge voltage in response to a precharge signal; wherein

the precharge voltage has a first magnitude with respect to a reference voltage, and

the read drive voltage has a second magnitude with respect to the reference voltage.

18. The memory device of claim 7 , wherein:

the memory elements are programmable between

a first state that provides a first change in property response to the sense conditions, and

a second state having a second change in property response under the sense conditions that is different from the first change in property response; and

the reference circuit provides a reference change in property response different from the first and second change in property responses.