Method and system to access memory
View Patent ↗This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.
1. An apparatus, comprising:
a memory device;
an Input/Output (I/O) buffer; and
a latency programming circuit coupled to the memory device and the I/O buffer to store a plurality of values of a number of dummy bytes received at the memory device prior to transferring data from the memory device during a read operation,
wherein the latency programming circuit comprises an address counter, a programmable latency register, and a comparator.
2. The apparatus of claim 1 , wherein the number of dummy bytes corresponds to a time delay before transferring data from the memory device to the I/O buffer.
3. The apparatus of claim 1 , wherein the programmable latency register is to store a plurality of values of the number of dummy bytes associated with a plurality of operational codes.
4. The latency programming circuit of claim 1 , wherein the comparator is configured to send an output enable signal to the I/O buffer based on information received from the address counter and the programmable latency register.
5. The latency programming circuit of claim 1 , wherein the programmable latency register is reset upon power up of the memory device.
6. The apparatus of claim 1 , wherein the memory device includes a FLASH memory.
7. The apparatus of claim 1 , wherein the programmable latency register is re-programmed upon power-up.
8. A method of configuring a time delay to be provided during a read operation, the method comprising:
selecting a stored value from a configuration register having a plurality of stored values associated with dummy bytes, wherein the number of dummy bytes corresponds to the time delay; and
associating the number of dummy bytes to a read command,
wherein selecting the value from the configuration register includes selecting the number of dummy bytes required for a time delay, before data is read from the memory array and after a read command is provided.