Circuits having programmable impedance elements
View Patent ↗An integrated circuit (IC) device may include a first portion having a plurality of volatile memory cells; and a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable more than once between different resistance values. A memory device may also include variable impedance elements accessible by access bipolar junction transistors (BJTs) having at least a portion formed by a semiconductor layer formed over a substrate. A memory device may also include a plurality of memory elements that each includes a dielectric layer formed between a first and second electrode, the dielectric layer including a solid electrolyte with a soluble metal having a mobility less than that of silver in a germanium disulfide.
1. An integrated circuit (IC) device, comprising:
a first portion having a plurality of volatile memory cells; and
a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable between different resistance values more than one time; wherein
the volatile memory cells include one-transistor (1-T) dynamic random access memory (DRAM) cells.
2. The IC device of claim 1 , wherein:
the first portion and second portion include transistors of the same type.
3. The IC device of claim 2 , wherein:
the transistors of the first portion and second portion have a same layout.
4. The IC device of claim 2 , wherein:
the second portion includes the resistive elements being formed over the transistors.
5. The IC device of claim 1 , wherein:
the volatile memory cells and the nonvolatile memory cells are one-transistor memory cells, each including only one active device.
6. The IC device of claim 1 , wherein:
the volatile memory cells include capacitors formed over the transistors; and
the nonvolatile memory cells include the resistive elements formed over the transistors.
7. The IC device of claim 1 , further including:
a controller circuit having a direct data transfer path to memory cells of the first portion, and no direct data transfer path to memory cells of the second portion.
8. The IC device of claim 7 , wherein:
the first portion, second portion, and a controller circuit are formed in a same contiguous integrated circuit substrate.
9. The IC device of claim 1 , wherein:
the volatile memory cells of the first portion are coupled to first bit lines having a first pitch; and
the nonvolatile memory cells of the second portion are coupled to second bit lines having the first pitch.
10. The IC device of claim 1 , wherein:
the nonvolatile memory cells include 1-T resistive memory cells, each including at least one programmable metallization cell having a solid ion conductor material.
11. An IC device, comprising:
a first portion having a plurality of volatile memory cells; and
a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable between different resistance values more than one time; wherein
the volatile memory cells include static random access memory (SRAM) cells; and
the nonvolatile memory cells include programmable metallization cells having a solid ion conductor material.
12. The IC device of claim 1 , further including:
the first portion further includes first bit lines coupled the volatile memory cells;
the second portion further includes second bit lines coupled to the nonvolatile memory cells; and
a gate circuit configured to selectively connect first bit lines to second bit lines.
13. The IC device of claim 12 , further including:
the gate circuit is configured to isolate a capacitance of the second bit lines from that of the first bit lines.
14. The IC device of claim 12 , further including:
the gate circuit is configured to isolate the second bit lines from the first bit lines when data values are programmed into the nonvolatile memory cells.
15. The IC device of claim 1 , further including:
the first portion further includes first bit lines coupled the volatile memory cells;
the second portion further includes second bit lines coupled to the nonvolatile memory cells; and
decoder circuits configured to selectively map first bit lines to second bit lines in response to at least a portion of an address value.
16. The IC device of claim 1 , further including:
the first portion further includes first bit lines coupled the volatile memory cells;
the second portion further includes second bit lines coupled to the nonvolatile memory cells; and
encoder/decoder circuits configured to encode data values stored in the first portion into encoded values for storage in the second portion, and decode encoded data values stored in the second portion into data values for storage in the first portion.
17. The IC device of claim 1 , further including:
a control circuit configured to activate a load indication in response to predetermined conditions of the IC device; and
the first portion is configured to read data values stored in nonvolatile memory cells of the second portion into volatile memory cells of the first portion in response to the load indication.
18. An IC device, comprising:
a first portion having a plurality of volatile memory cells;
a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable between different resistance values more than one time; and
a power supply management circuit configured to activate a back-up indication in response to predetermined power conditions of the IC device; wherein
the second portion is configured to program data values stored in volatile memory cells of the first portion into nonvolatile memory cells of the second portion in response to the back-up indication.
19. The IC device of claim 18 , further including:
a back-up power supply configured to supply power to the second portion to enable the data values stored in volatile memory cells to be programmed into the nonvolatile memory cells of the second portion in the absence of a regular power supply.