Circuits and methods for placing programmable impedance memory elements in high impedance states
View Patent ↗A memory device can include a load circuit coupled in series with at least one memory element between two nodes and configured to enable a programming current to flow through the memory element to lower its impedance, and configured to enable an erase current to flow through the element in a direction opposite to the program current, the erase current varying in response to an erase voltage applied across the two nodes as the memory element impedance increases.
1. A memory device, comprising:
a load circuit coupled in series with at least one memory element between two nodes and comprising a first controllable current path and at least one second controllable current path in parallel with the first controllable current path and
configured to enable a programming current to flow through the first current path and the memory element to lower its impedance, and
configured to enable an erase current to flow through the second current path and the element in a direction opposite to the program current, the erase current varying in response to an erase voltage applied across the two nodes as the memory element impedance increases.
2. The memory device of claim 1 , wherein:
the load circuit comprises an insulated gate field effect transistor
configured to enable the programming current to flow through a transistor channel by operation of a depletion region created by a control gate voltage, and
configured to enable the erase current to flow through a forward biased p-n junction formed by a source or drain and body of the transistor.
3. The memory device of claim 1 , wherein:
the load circuit comprises an insulated gate field effect transistor configured to enable the erase current to flow through a transistor channel, the transistor operating in a linear region of operation and having a sufficiently large channel to allow enough erase current to increase the impedance of the element.
4. The memory device of claim 1 , wherein:
the load circuit comprises an insulated gate field effect transistor
configured to enable the programming current to flow through a transistor channel by operation of a depletion region created by a control gate voltage, and
configured in a snapback mode of operation to enable the erase current to flow through the transistor.
5. The memory device of claim 1 wherein:
the load circuit is
configured to provide a maximum programming current of magnitude Imax_prog; and
configured to provide a maximum erase current of magnitude Imax_erase; wherein
Imax_erase is no less than Imax_prog.
6. The memory device of claim 1 , wherein:
the load circuit is configured to automatically cease substantially all erase current in response to the memory element impedance increasing to a predetermined limit.
7. The memory device of claim 6 , wherein:
the load circuit comprises a p-n junction diode that ceases passing the erase current once an increase in memory element resistance results in a voltage across the p-n junction diode being less than its threshold voltage.
8. The memory device of claim 1 , wherein:
the second controllable current path comprises a switch element in series with a diode.
9. The memory device of claim 1 , wherein:
the memory element comprises a solid electrolyte.
10. The memory device of claim 1 , wherein:
the memory element is
programmable to a resistance of less than about 10 kohms by application of the programming current,
erasable to a first resistance in the range of about 10 kohms to 750 kohms by application of a first erase voltage,
erasable to a second resistance in the range of about 750 kohms to 8 Mohms by application of a second erase voltage,
erasable to a third resistance greater than about 8 Mohms.
11. A memory device, comprising:
a plurality of memory elements reversibly programmed between different impedance states; and
a plurality of access devices, at least one access device coupled to each memory element configurable to couple the memory element to a bit line in response to a signal at a control gate in a read mode, and provide a first current path for increasing the impedance of the element in an erase mode;
wherein the first current path is not controlled via the control gate.
12. The memory device of claim 11 , wherein:
each memory element comprises a solid electrolyte.
13. The memory device of claim 11 , wherein:
each access device comprises a metal-oxide-semiconductor (MOS) type transistor, and the first current path comprises a forward biased source/drain-body junction of the MOS type transistor.
14. The memory device of claim 13 , further including:
a substrate region doped to a first conductivity type;
a first well formed in the substrate region and doped to a second conductivity type; and
a second well formed in the first well and doped to the first conductivity type; wherein
at least one of the MOS type transistors is formed in the second well.
15. The memory device of claim 14 , wherein:
the first conductivity type is p-type;
the second conductivity type is n-type; and
the MOS type transistors are n-channel transistors.
16. The memory device of claim 11 , wherein:
each access device is further configured to provide a second current path for decreasing the impedance of the element, the second current path comprising the channel of the MOS type transistor.
17. The memory device of claim 11 , wherein:
each access device is selected from the group of: a bipolar junction transistor and a junction field effect transistor.
18. A method, comprising:
generating an erase current of at least one magnitude through an element that increases its impedance by application of at least one erase voltage, the erase current increasing in magnitude as the erase voltage increases in magnitude, and self-limiting the erase current by automatically stopping essentially all of the erase current when the element reaches a predetermined impedance without application of a control signal; and
generating a programming current through the element that decreases its impedance by application of at least on program voltage, the programming current flowing in the opposite direction to the erase current.
19. The method of claim 18 , wherein:
generating the erase current includes generating one of a plurality of erase currents by application of one of a plurality of erase voltages to place the element in one of a plurality of different erase impedance states; wherein
the programming current places the element in at least one program impedance state having a lower impedance than the erase impedance states.
20. The method of claim 18 , wherein:
generating the erase current includes forward biasing at least one p-n junction in an access device coupled to the element.
21. The method of claim 20 , wherein:
the access device comprises a metal-oxide-semiconductor (MOS) type transistor; and
generating at least one programming current includes inverting a channel in the MOS type transistor.
22. The method of claim 20 , wherein:
generating the erase current includes forward biasing different numbers of p-n junctions to vary the erase current to erase the element to different higher impedance states.
23. The method of claim 18 , wherein:
generating the erase current includes placing a metal-oxide-semiconductor (MOS) type transistor in a snapback mode of operation.