Method for operating an integrated circuit having a resistivity changing memory cell
View Patent ↗A method for operating a resistivity changing memory including applying a programming voltage to a resistivity changing memory cell to define a programmed state and applying a refresh voltage to the resistivity changing memory cell for maintaining the programmed state of the resistivity changing memory cell. In one embodiment, the refresh voltage is less than the programming voltage.
1. A memory circuit, comprising:
a plurality of memory cells adapted to selectively develop and diminish a conductive path depending upon an applied electrical field;
a refresh unit coupled to the memory cells and configured to apply a refresh voltage to at least a subset of the memory cells in response to predetermined conditions, and including a detection unit configured to read out contents of memory cells in response to the application of the refresh voltage; and
a read unit coupled to the memory cells and configured to read out data from selected memory cells by application of a read voltage; wherein
the read voltage has a different magnitude than the refresh voltage.
2. The memory circuit of claim 1 , wherein:
each memory cell comprises a solid electrolyte and is adapted to selectively develop and diminish the conductive path through the solid electrolyte depending upon the applied electrical field.
3. The memory circuit of claim 1 , wherein:
the detection unit is shared by the refresh unit and the read unit, and is further configured to read out contents of memory cells in response to the application of the read voltage.
4. The memory circuit of claim 1 , further including:
a write unit configured to selectively apply at least one programming voltage to at least a portion of the memory cells in response to read data values generated from the detection unit; wherein
the programming voltage has a different magnitude than the refresh voltage and the read voltage.
5. The memory circuit of claim 1 , wherein:
the refresh voltage has a greater magnitude than the read voltage.
6. The memory circuit of claim 1 , wherein:
the refresh voltage has the same polarity as the read voltage.
7. The memory circuit of claim 1 , wherein:
the refresh unit applies the refresh voltage to at least a subset of the memory cells in response to a power-on of the memory circuit.
8. The memory circuit of claim 1 , wherein:
the refresh unit further includes a timer circuit, and is configured to apply the refresh voltage to at least a subset of the memory cells in response to an output of the timer circuit.
9. The memory circuit of claim 1 , further including:
a write unit configured to apply at least one write voltage to at least a portion of the memory cells; wherein
the at least one write voltage has a different magnitude than the refresh voltage and the read voltage.
10. The memory circuit of claim 9 , wherein:
the at least one write voltage includes a programming voltage and an erase voltage; wherein
the programming voltage and erase voltage have different magnitudes than the refresh voltage and read voltage, and the erase voltage has a different polarity across the memory cells than the read, refresh and program voltages.
11. A method, comprising:
determining if a predetermined time interval has passed;
if the time interval has not passed, applying a read voltage to at least a subset of the memory cells to detect states of the memory cells; and
if the time interval has passed, applying a refresh voltage to at least a subset of memory cells to detect states of the memory cells, the memory cells being adapted to selectively develop and diminish a conductive path depending upon an applied electrical field; wherein
the refresh voltage has a greater magnitude than a read voltage applied to read data from the memory cells.
12. The method of claim 11 , wherein:
the memory cells are adapted to develop and diminish conductive paths through an electrolyte material.
13. The method of claim 11 , wherein:
the refresh voltage is applied to at least a subset of the memory cells before each read-out operation.
14. The method of claim 11 , further including:
selectively applying a program voltage to a memory cell according to the detected state of the memory cell; wherein
the program voltage has a greater magnitude than the refresh voltage.
15. The method of claim 11 , further including:
applying different write voltages to the memory cells to develop or diminish conductive paths through the memory cells in response to write data; wherein
at least one of the write voltages has a greater magnitude than the refresh voltage.
16. A method, comprising:
in response to a write instruction to program memory cells, applying a refresh voltage to at least a subset of the memory cells, the memory cells being adapted to selectively develop and diminish a conductive path depending upon an applied electrical field;
detecting the state of at least a subset of the memory cells with the application of the refresh voltage; and
selectively applying the program voltage to a memory cell according to the detected state of the memory cell; wherein
the refresh voltage has a smaller magnitude than a program voltage applied to develop conductive paths in the memory cells, and a greater magnitude than a read voltage applied to determine states of the memory cells.
17. The method of claim 16 , wherein:
the memory cells are adapted to develop and diminish conductive paths through an electrolyte material.
18. A method, comprising:
applying a refresh voltage to at least a subset of memory cells, each memory cell having an electrolyte between two electrodes and being programmable between at least a first state and a second state, the second state being more time stable than the first state;
detecting the state of at least a subset of the memory cells with the application of the refresh voltage; and
reading data from at least some of the memory cells by application of a read voltage; wherein
the refresh voltage has a smaller magnitude than at least one program voltage applied to place a memory element in one of the states, the read voltage has a smaller magnitude than the refresh voltage, and
the refresh voltage reinforces the first state.
19. The method of claim 18 , wherein:
the refresh voltage reinforces the first state without compromising the second state.
20. The method of claim 18 , wherein:
the refresh voltage is applied to at least a subset of the memory cells before each read-out operation.
21. The method of claim 18 , further including:
programming a memory cell to the first state by applying a first program voltage; and
selectively applying the first program voltage to a memory cell according to the detected state of the memory cell.
22. A method, comprising:
detecting a state of memory cells by application of a detect voltage; and
selectively applying a second program voltage and not applying a first program voltage to a memory cell according to the detected state of the memory cell; wherein
each memory cell is programmable between at least a first state and a second state by developing and diminishing a conductive path through an electrolyte material,
application of the first program voltage places the memory cell in the first state and application of the second program voltage places the memory cell in the second state,
the first state is more time-stable than the second state; and
the detect voltage is a refresh voltage having a magnitude less than the second program voltage, but greater than a read voltage applied to read data from the memory cell, and the refresh voltage reinforces the second state.