IP Library Granted Patent US 8,437,171
Granted Patent B1
US 8,437,171 · App. 12/980,752 · Granted May 7, 2013

Methods and circuits for temperature varying write operations of programmable impedance elements

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Quick Facts
Patent No.
US 8,437,171
App. No.
12/980,752
Granted
May 7, 2013
Kind
B1
Abstract

A circuit may include an array having a number of programmable impedance elements that may be placed into at least two different impedance states in a write operation; and a write circuit that applies temperature varying write conditions to the array in a write operation.

Claims (68)

1. A circuit, comprising:

an array that includes a number of programmable impedance elements that may be placed into at least two different impedance states in a write operation; and

a write circuit that applies temperature varying write conditions to the array in the write operation and includes a temperature dependent reference circuit that generates a temperature reference value in response to a sensed temperature.

2. The circuit of claim 1 , wherein:

the write circuit comprises

access circuits that apply at least one electrical write value to the programmable impedance elements, the at least one electrical write value varying in response to the temperature reference value.

3. The circuit of claim 1 wherein:

the write circuit comprises

the temperature dependent reference circuit generating a write voltage that varies in response to the sensed temperature, and

access circuits that apply the write voltage to the programmable impedance elements.

4. The circuit of claim 1 wherein:

the write circuit varies an amplitude and duration of electrical write conditions in response to the sensed temperature to deliver a substantially constant write time over an operating temperature range of a device containing the circuit.

5. The circuit of claim 1 , wherein:

the write circuit further includes

a pulse generator coupled to access circuits that generates at least one electrical pulse that varies in response to variations in the sensed temperature, and

the access circuits apply the at least one electrical pulse to the programmable impedance elements.

6. The circuit of claim 5 , wherein:

the at least one pulse has an amplitude that varies in response to variations in the sensed temperature.

7. The circuit of claim 6 , wherein:

the at least one pulse has an essentially constant duration regardless of temperature.

8. The circuit of claim 5 , wherein:

the at least one pulse has a duration that varies in response to variations in the sensed temperature.

9. The circuit of claim 1 , wherein

the at least two impedance states include

a first impedance state that is substantially constant during a read operation, and

a second impedance state having a relative lower impedance than the first impedance state.

10. A circuit, comprising:

a temperature sense circuit that generates a temperature value in response to a sensed temperature; and

a write circuit configured to apply electrical signals having different polarities across electrodes of memory elements to write different data values, the electrical signal of at least one polarity varying as the temperature value varies.

11. The circuit of claim 10 , wherein:

each memory element comprises an ion conducting layer disposed between two electrodes.

12. The circuit of claim 10 , wherein:

each memory element comprises a programmable metallization cell (PMC).

13. The circuit of claim 10 , wherein:

the write circuit applies program electrical signals having a first polarity across two electrodes of a memory element to write a first data value in a memory element, and applies erase electrical signals having a second polarity cross the two electrodes of a memory element to write a second data value in a memory element.

14. The circuit of claim 13 , wherein:

the write circuit varies the program electrical signals as the temperature value varies, and does not vary the erase electrical signals as the temperature value varies.

15. The circuit of 10 , wherein:

the memory elements are included in an array of memory cells, each memory cell comprising a memory element coupled to an access device; and

each access device includes a controllable impedance path coupled between its corresponding memory element and a bit line, and a control terminal coupled to a word line.

16. The circuit of 10 , wherein:

the write circuit varies a write signal duration in response to temperature.

17. The circuit of 10 , wherein:

the write circuit varies a write electrical signal duration and amplitude to provide a substantially constant write time over an operating temperature range of a device containing the circuit.

18. A method comprising

detecting a write operation to a memory device having a plurality of programmable elements that may be programmed between at least two impedance responses by electrical signals of different polarities across electrodes of the programmable elements; and

performing a temperature varying write operation to at least selected of the programmable elements including setting an electrical write value based on a sensed temperature.

19. The method of claim 18 , wherein:

performing the temperature varying write operation includes

writing data to at least selected of the programmable elements with the electrical write value.

20. The method of claim 18 , wherein:

detecting the write operation includes detecting at least a program operation or an erase operation;

performing the temperature varying write operation includes

in a program operation,

generating the at least one program electrical signal that varies in response to the sensed temperature, and

applying the at least one program electrical signal to programmable elements according to input write data values,

in an erase operation, applying at least one erase electrical signal to programmable elements without regard to input write data values.

21. The method of claim 18 , wherein:

performing a temperature varying write operation includes

applying at least one write electrical pulse to at least one programmable element, the at least one write pulse having a duration that varies according to a sensed temperature.

22. The method of claim 18 , wherein:

performing a temperature varying write operation includes

applying a plurality of write electrical pulses to at least one programmable element, the number of write pulses varying according to a sensed temperature.

23. The method of claim 18 , wherein:

performing a temperature varying write operation includes

applying at least one write electrical pulse to at least one programmable element, the at least one write pulse having an amplitude that varies according to a sensed temperature.

24. The method of claim 18 , wherein:

performing a temperature varying write operation includes varying write pulse amplitude and duration to maintain a substantially constant write time regardless of the sensed temperature.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2023
From: RENESAS DESIGN US INC. (FORMERLY KNOWN AS DIALOG SEMICONDUCTOR US INC. AS SUCCESSOR-IN-INTEREST TO ADESTO TECHNOLOGIES CORPORATION AND ARTEMIS ACQUISITION, LLC)
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 063118/0352 →
RELEASE OF SECURITY INTEREST Recorded Sep 24, 2019
From: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 050480/0836 →
RELEASE OF SECURITY INTEREST Recorded May 9, 2019
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 049125/0970 →
SECURITY INTEREST Recorded May 8, 2018
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
Reel/Frame 046105/0731 →
RELEASE OF SECURITY INTEREST Recorded Oct 3, 2017
From: WESTERN ALLIANCE BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 044219/0610 →
SECURITY INTEREST Recorded May 22, 2015
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 035754/0580 →
RELEASE OF SECURITY INTEREST Recorded Oct 15, 2013
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 031414/0232 →
SECURITY AGREEMENT Recorded Oct 7, 2013
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: BRIDGE BANK, NATIONAL ASSOCIATION
Reel/Frame 031371/0581 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2012
From: GILBERT, NAD EDWARD
To: ADESTO TECHNOLOGIES CORPORATION
Reel/Frame 029396/0722 →
SECURITY AGREEMENT Recorded Oct 8, 2012
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 029090/0922 →