IP Library Granted Patent US 8,866,122
Granted Patent B1
US 8,866,122 · App. 13/517,653 · Granted Oct 21, 2014

Resistive switching devices having a buffer layer and methods of formation thereof

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Quick Facts
Patent No.
US 8,866,122
App. No.
13/517,653
Granted
Oct 21, 2014
Kind
B1
Abstract

In one embodiment, a resistive switching device includes a bottom electrode, a switching layer, a buffer layer, and a top electrode. The switching layer is disposed over the bottom electrode. The buffer layer is disposed over the switching layer and provides a buffer of ions of a memory metal. The buffer layer includes an alloy of the memory metal with an alloying element, which includes antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic. The top electrode is disposed over the buffer layer and provides a source of the memory metal.

Claims (62)

1. A resistive switching device comprising:

a bottom electrode;

a switching layer disposed over the bottom electrode;

a buffer layer disposed over the switching layer, the buffer layer providing a buffer of ions of a memory metal, the buffer layer comprising an alloy of the memory metal with an alloying element comprising antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic, wherein the buffer layer comprises a thickness of about 1 nm to about 50 nm; and

a top electrode disposed over the buffer layer, the top electrode providing a source of the memory metal.

2. The device of claim 1 , further comprising a cap layer disposed between the buffer layer and the top electrode, the cap layer forming a barrier to a reactive element in the buffer layer.

3. The device of claim 1 , wherein the top electrode comprises a second alloying element comprising antimony, tin, bismuth, aluminum, arsenic, germanium, and silicon.

4. The device of claim 3 , wherein the alloying element and the second alloying element are the same element.

5. The device of claim 1 , wherein the top electrode comprises a graded profile of a second alloying element.

6. The device of claim 5 , wherein the alloying element and the second alloying element are the same element.

7. The device of claim 1 , wherein the buffer layer comprises a graded profile of the alloying element.

8. The device of claim 1 , wherein the buffer layer comprises a second alloying element, the second alloying element comprising tellurium or sulfur, wherein the second alloying element has a graded profile, and wherein the second alloying element has a peak concentration at an interface between the switching layer and the buffer layer.

9. The device of claim 8 , wherein the second alloying element has a minimum concentration at an interface between the top electrode and the buffer layer.

10. A resistive switching device comprising:

a bottom electrode;

a switching layer disposed over the bottom electrode;

a buffer layer disposed over the switching layer, the buffer layer providing a buffer of ions of a memory metal, the buffer layer comprising a reactive element;

a cap layer disposed over the buffer layer, the cap layer forming a barrier to the reactive element in the buffer layer; and

a top electrode disposed over the buffer layer, the top electrode providing a source of the memory metal.

11. The device of claim 10 , wherein the buffer layer comprises an alloy of the memory metal with an alloying element comprising antimony, tin, bismuth, aluminum, arsenic, germanium, and silicon.

12. The device of claim 10 , wherein the reactive element comprises tellurium or sulfur.

13. The device of claim 10 , wherein the cap layer comprises a thickness of less than 10 nm.

14. The device of claim 10 , wherein the cap layer comprises a thickness of about 0.5 nm to about 10 nm.

15. The device of claim 10 , wherein the cap layer comprises a layer of antimony, germanium, or tin.

16. The device of claim 10 , wherein the cap layer comprises a metal alloy comprising an alloying element and an element of the top electrode.

17. A method of forming a resistive switching device, the method comprising:

forming a bottom electrode in a first insulating layer;

forming a second insulating layer over the first insulating layer;

forming a switching layer over the bottom electrode in the second insulating layer;

forming a buffer layer over the switching layer in the second insulating layer, the buffer layer providing a buffer of ions of a memory metal, the buffer layer comprising an alloy of the memory metal with an alloying element comprising antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic, wherein forming the buffer layer comprises forming a layer having a thickness of about 1 nm to about 50 nm; and

forming a top electrode over the buffer layer in a third insulating layer, the top electrode providing a source of the memory metal.

18. The method of claim 17 , wherein the second insulating layer and the third insulating layer are formed in a common process step.

19. The method of claim 17 , further comprising forming a cap layer between the buffer layer and the top electrode, the cap layer forming a barrier to a reactive element in the buffer layer.

20. The method of claim 17 , wherein forming the top electrode comprises forming an alloy comprising a second alloying element comprising antimony, tin, bismuth, aluminum, arsenic, germanium, and silicon.

21. The method of claim 20 , wherein the alloying element and the second alloying element are the same element.

22. The method of claim 17 , wherein forming the top electrode comprises a graded profile of a second alloying element.

23. The method of claim 22 , wherein the alloying element and the second alloying element are the same element.

24. The method of claim 17 , wherein forming the buffer layer comprises forming a graded profile of the alloying element.

25. The method of claim 17 , wherein forming the buffer layer comprises forming an alloy comprising a second alloying element, the second alloying element comprising tellurium or sulfur, wherein the second alloying element has a graded profile, and wherein the second alloying element has a peak concentration at an interface between the switching layer and the buffer layer.

26. The method of claim 25 , wherein the second alloying element has a minimum concentration at an interface between the top electrode and the buffer layer.

27. A resistive switching device comprising:

a bottom electrode;

a switching layer disposed over the bottom electrode;

a buffer layer disposed over the switching layer, the buffer layer providing a buffer of ions of a memory metal; and

a top electrode disposed over the buffer layer, the top electrode providing a source of the memory metal, the top electrode comprising an alloying element comprising antimony, tin, bismuth, aluminum, arsenic, germanium, and silicon.

28. The device of claim 27 , wherein the alloying element has a graded profile within the top electrode.

29. The device of claim 28 , wherein a concentration of the alloying element has a peak concentration at about an interface of the top electrode with the buffer layer.

30. The device of claim 28 , wherein the graded profile extends over at least 10 nm.

31. The device of claim 28 , wherein the graded profile has a thickness of about 1 nm to about 10 nm.

32. The device of claim 28 , wherein the alloying element changes in concentration within the graded profile by at least 100 times within about 0.5 to about 0.1 of a thickness of the top electrode from an interface of the top electrode with the buffer layer.

33. A resistive switching device comprising:

a bottom electrode;

a switching layer disposed over the bottom electrode;

a buffer layer disposed over the switching layer, the buffer layer providing a buffer of ions of a memory metal; and

a top electrode disposed over the buffer layer, the top electrode providing a source of the memory metal and comprising an alloying element, wherein the alloying element has a graded profile within the top electrode.

34. The device of claim 33 , wherein the buffer layer comprises a graded profile of the alloying element.

35. The device of claim 33 , wherein the buffer layer comprises a second alloying element, the second alloying element comprising tellurium or sulfur, wherein the second alloying element has a graded profile, and wherein the second alloying element has a peak concentration at an interface between the switching layer and the buffer layer.

36. A resistive switching device comprising:

a bottom electrode;

a switching layer disposed over the bottom electrode;

a buffer layer disposed over the switching layer, the buffer layer providing a buffer of ions of a memory metal, the buffer layer comprising an alloy of the memory metal with an alloying element comprising antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic; and

a top electrode disposed over the buffer layer, the top electrode providing a source of the memory metal, wherein the top electrode comprises a second alloying element comprising antimony, tin, bismuth, aluminum, arsenic, germanium, and silicon.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2023
From: RENESAS DESIGN US INC. (FORMERLY KNOWN AS DIALOG SEMICONDUCTOR US INC. AS SUCCESSOR-IN-INTEREST TO ADESTO TECHNOLOGIES CORPORATION AND ARTEMIS ACQUISITION, LLC)
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 063118/0352 →
RELEASE OF SECURITY INTEREST Recorded Sep 24, 2019
From: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 050480/0836 →
RELEASE OF SECURITY INTEREST Recorded May 9, 2019
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 049125/0970 →
SECURITY INTEREST Recorded May 8, 2018
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
Reel/Frame 046105/0731 →
SECURITY INTEREST Recorded May 22, 2015
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 035754/0580 →
RELEASE OF SECURITY INTEREST Recorded Oct 15, 2013
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 031414/0232 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF ASSIGNEE PREVIOUSLY RECORDED ON REEL 028376 FRAME 0344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNOR'S INTEREST (SEE DOCUMENT FOR DETAILS).. Recorded Oct 12, 2012
From: LEE, WEI TI; GOPALAN, CHAKRAVARTHY; MA, YI; TSAI, KUEI-CHANG; SHIELDS, JEFFREY; WANG, JANET
To: ADESTO TECHNOLOGIES CORPORATION
Reel/Frame 029124/0442 →
SECURITY AGREEMENT Recorded Oct 8, 2012
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 029090/0922 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2012
From: LEE, WEI TI; GOPALAN, CHAKRAVARTHY; MA, YI; TSAI, KUEI-CHANG; SHIELDS, JEFFREY; WANG, JANET
To: ADESTO TECHNOLOGIES CORPORATION
Reel/Frame 028376/0344 →