Circuits and methods having programmable impedance elements

1. An integrated circuit (IC) device, comprising:

a plurality of memory cells that store configuration data, each memory cell including a latch circuit and at least one programmable resistance element, each memory cell being coupled between a first supply voltage and a virtual supply node;

a re-configurable circuit coupled to the memory cells having a function that varies in response to the configuration data; and

a mode switch circuit having switchable paths that couple the virtual supply node between at least a second supply voltage and a write voltage, the mode switch configurable to couple the virtual supply node to the write voltage to change the programmable resistance element to a first resistance value, and to couple the virtual supply node to the second supply voltage to change the programmable resistance element to a second resistance value; wherein the second supply voltage is different than the write voltage.

2. The IC device of claim 1 , wherein:

a potential difference between a write voltage and the first supply voltage is sufficient to change the at least one programmable resistance element between the first resistance value and the second resistance value.

3. The IC device of claim 1 , wherein

each memory cell includes

the latch circuit having at least a first latch node and a second latch node that can latch between at least two stable states,

a first programmable resistance element coupled between the first latch node and the virtual supply node, and

a second programmable resistance element coupled between the second latch node and the virtual supply node.

4. The IC device of claim 3 , wherein

the first and second programmable resistance elements comprise programmable resistance cells (PMCs) having cathodes coupled to the latch circuit and anodes coupled to the virtual supply node.

5. The IC device of claim 3 , wherein

the first and second programmable resistance elements comprise programmable resistance cells (PMCs) having anodes coupled to the latch circuit and cathodes coupled to the virtual supply node.

6. The IC device of claim 3 , wherein

the first and second programmable resistance elements comprise programmable resistance cells (PMCs) with one PMC having an anode coupled to the latch circuit and a cathode coupled to the virtual supply node, and the other PMC having a cathode coupled to the latch circuit and an anode coupled to the virtual supply node.

7. The IC device of claim 1 , wherein

the mode switch circuit further includes a switchable path that couples the virtual supply node to a high impedance connection.

8. The IC device of claim 1 , wherein

each memory cell includes

the latch circuit having at least a first latch node and a second latch node that latch between at least two stable states,

a programmable resistance element coupled between the first latch node a virtual power supply node, and

a static resistance element coupled between the second latch node and the virtual power supply node, wherein

the programmable resistance element is writable between at least a first resistance that is less than that of the static resistance element and a second resistance that is greater than that of the static resistance element.

9. The IC device of claim 1 , further including

each memory cell is coupled to at least one of a plurality of bit lines; and

write circuits coupled to the bit lines and configured to drive bit lines to predetermined bit line write voltages in a write operation in response to write data;

wherein

application of the bit line write voltage to a bit line and the predetermined supply voltage to the virtual supply node is sufficient to establish a first resistance value in the at least one programmable resistance element.

10. The IC device of claim 1 , wherein

each memory cell includes

a first latching active device having a first control terminal coupled to a second latch node and a first controlled impedance path coupled between a first latch node and the at least one programmable resistance element, and

a second latching active device having a second control terminal coupled to the first latch node and a second controlled impedance path coupled to the second latch node.

11. The IC device of claim 1 , wherein:

the re-configurable circuit is selected from the group of: a programmable crosspoint connection circuit, a programmable multiplexer, a programmable de-multiplexer, and a programmable logic circuit.

12. The IC device of claim 1 , wherein:

each memory cell includes

the latch circuits having transistors formed in a semiconductor substrate, and

the programmable resistance elements are formed over the substrate.

13. A method, comprising:

storing configuration data for a configurable circuit in memory circuits that each include a latch circuit and at least one programmable resistance element coupled between a first supply voltage and a virtual supply node that is written to at least one of a plurality of resistance values, including for each memory circuit,

driving a bit line to a bit line voltage corresponding to a data value to be stored, and

driving the at least one virtual supply node to a write supply voltage to write the programmable resistance element to a first resistance value, and driving the one virtual supply node to a second voltage to write the programmable resistance element to a second resistance value; wherein the second voltage is different from the write supply voltage.

14. The method of claim 13 , wherein

storing the configuration data includes, each memory circuit, having one programmable resistance element written to the first resistance value, and the second programmable resistance element written to a second resistance value.

15. The method of claim 13 , wherein

each memory circuit further includes a static resistance element, and the plurality of resistance values includes a first resistance value greater than that of the static resistance element and a second resistance value less than that of the static resistance element.

16. The method of claim 13 , further including

in response to a predetermined event, applying the configuration data to the configurable circuit to establish a function of the configurable circuit.

17. The method of claim 13 , wherein

storing the configuration data includes

driving a first programmable impedance element between different potentials while allowing a second programmable impedance element to float.

18. The method of claim 13 , further including

loading the configuration data into the memory circuits by driving bit lines connected to the memory circuits to values dependent upon the configuration data, and driving virtual supply nodes common to the memory circuits to a predetermined potential.

19. An integrated circuit (IC) device, comprising:

a plurality of memory cells that store configuration data, each memory cell including a latch circuit and first and second programmable resistance elements, each memory cell being coupled between a first supply voltage and a virtual supply node;

a re-configurable circuit coupled to the memory cells having a function that varies in response to the configuration data; and

a mode switch circuit having switchable paths that couple the virtual supply node between at least a second supply voltage and a write voltage; wherein

the first and second programmable resistance elements comprise programmable metallization cells (PMCs) having cathodes coupled to the latch circuit and anodes coupled to the virtual supply node; wherein the second voltage is different from the write supply voltage.

20. The IC device of claim 19 , wherein

the mode switch circuit further includes a switchable path that couples the virtual supply node to a high impedance connection.

21. The IC device of claim 19 , further including

each memory cell is coupled to at least one of a plurality of bit lines;

write circuits coupled to the bit lines and configured to drive bit lines to predetermined bit line write voltages in a write operation in response to write data; and

the virtual supply nodes are drivable to a predetermined supply voltage in a write operation; wherein

application of the bit line write voltage to a bit line and the predetermined supply voltage to the virtual supply node is sufficient to establish a first resistance value in the at least one programmable resistance element.

22. The IC device of claim 19 , wherein

each memory cell includes

a first latching active device having a first control terminal coupled to a second latch node and a first controlled impedance path coupled between a first latch node and the at least one programmable resistance element, and

a second latching active device having a second control terminal coupled to the first latch node and a second controlled impedance path coupled to the second latch node.

23. The IC device of claim 19 , wherein:

the re-configurable circuit is selected from the group of: a programmable crosspoint connection circuit, a programmable multiplexer, a programmable de-multiplexer, and a programmable logic circuit.

24. The IC device of claim 19 , wherein:

each memory cell includes

the latch circuits having transistors formed in a semiconductor substrate, and

the programmable resistance elements are formed over the substrate.

25. An integrated circuit (IC) device, comprising:

a plurality of memory cells that store configuration data, each memory cell including a latch circuit and first and second programmable resistance elements, each memory cell being coupled between a first supply voltage and a virtual supply node;

a re-configurable circuit coupled to the memory cells having a function that varies in response to the configuration data; and

a mode switch circuit having switchable paths that couple the virtual supply node between at least a second supply voltage and a write voltage; wherein

the first and second programmable resistance elements comprise programmable metallization cells (PMCs) having anodes coupled to the latch circuit and cathodes coupled to the virtual supply node; wherein the second voltage is different from the write supply voltage.

26. The IC device of claim 25 , wherein

the mode switch circuit further includes a switchable path that couples the virtual supply node to a high impedance connection.

27. The IC device of claim 25 , further including

each memory cell is coupled to at least one of a plurality of bit lines;

write circuits coupled to the bit lines and configured to drive bit lines to predetermined bit line write voltages in a write operation in response to write data; and

the virtual supply nodes are drivable to a predetermined supply voltage in a write operation; wherein

application of the bit line write voltage to a bit line and the predetermined supply voltage to the virtual supply node is sufficient to establish a first resistance value in the at least one programmable resistance element.

28. The IC device of claim 25 , wherein

each memory cell includes

a first latching active device having a first control terminal coupled to a second latch node and a first controlled impedance path coupled between a first latch node and the at least one programmable resistance element, and

a second latching active device having a second control terminal coupled to the first latch node and a second controlled impedance path coupled to the second latch node.

29. The IC device of claim 25 , wherein:

the re-configurable circuit is selected from the group of: a programmable crosspoint connection circuit, a programmable multiplexer, a programmable de-multiplexer, and a programmable logic circuit.

30. The IC device of claim 25 , wherein:

each memory cell includes

the latch circuits having transistors formed in a semiconductor substrate, and

the programmable resistance elements are formed over the substrate.

31. An integrated circuit (IC) device, comprising:

a plurality of memory cells that store configuration data, each memory cell including a latch circuit and first and second programmable resistance elements, each memory cell being coupled between a first supply voltage and a virtual supply node;

a re-configurable circuit coupled to the memory cells having a function that varies in response to the configuration data; and

a mode switch circuit having switchable paths that couple the virtual supply node between at least a second supply voltage and a write voltage; wherein

the first and second programmable resistance elements comprise programmable metallization cells (PMCs) with one PMC having an anode coupled to the latch circuit and a cathode coupled to the virtual supply node, and the other PMC having a cathode coupled to the latch circuit and an anode coupled to the virtual supply node; wherein the second voltage is different from the write supply voltage.

32. The IC device of claim 31 , wherein

the mode switch circuit further includes a switchable path that couples the virtual supply node to a high impedance connection.

33. The IC device of claim 31 , further including

each memory cell is coupled to at least one of a plurality of bit lines;

write circuits coupled to the bit lines and configured to drive bit lines to predetermined bit line write voltages in a write operation in response to write data; and

the virtual supply nodes are drivable to a predetermined supply voltage in a write operation; wherein

application of the bit line write voltage to a bit line and the predetermined supply voltage to the virtual supply node is sufficient to establish a first resistance value in the at least one programmable resistance element.

34. The IC device of claim 31 , wherein

each memory cell includes

a first latching active device having a first control terminal coupled to a second latch node and a first controlled impedance path coupled between a first latch node and the at least one programmable resistance element, and

a second latching active device having a second control terminal coupled to the first latch node and a second controlled impedance path coupled to the second latch node.

35. The IC device of claim 31 , wherein:

the re-configurable circuit is selected from the group of: a programmable crosspoint connection circuit, a programmable multiplexer, a programmable de-multiplexer, and a programmable logic circuit.

36. The IC device of claim 31 , wherein:

each memory cell includes

the latch circuits having transistors formed in a semiconductor substrate, and

the programmable resistance elements are formed over the substrate.