Automatic reference voltage trimming technique
View Patent ↗In one set of embodiments, trimming of a reference, which may be a bandgap reference and which is configured on an integrated circuit, may be controlled by an algorithm executed by logic circuitry also configured on the integrated circuit. The bandgap reference may be configured to generate a reference voltage provided to an analog to digital converter (ADC) comprised in a temperature sensor that may also be configured on the integrated circuit. The logic circuitry may be configured to execute one or more of a variety of test algorithms, for example a Successive Approximation Method or remainder processing, that are operable to adjust values of reference trim bits used in trimming the bandgap reference. A tester system configured to perform testing of the integrated circuit may initiate execution of the test algorithm, thereby initiating the trimming process, and may wait for the test algorithm to complete within a previously defined amount of time, or may poll the logic circuitry to determine when the trimming process is complete.
1. An integrated circuit comprising:
a first component operable to generate a reference value; and
a second component operable to execute a test algorithm configured to control a trimming of the first component according to an external control value to adjust the reference value; and
an analog to digital converter (ADC), wherein the reference value is a reference voltage used by the ADC to determine a voltage range of an input signal converted by the ADC;
wherein the second component is operable to begin executing the test algorithm in response to receiving a start signal from a tester apparatus configured to perform testing on the integrated circuit.
2. The integrated circuit of claim 1 , wherein the ADC is comprised in a precision temperature sensor, and wherein in adjusting the reference value the second component operates to calibrate the precision temperature sensor.
3. The integrated circuit of claim 1 , wherein the second component is operable to adjust the reference value according to a specified code corresponding to the external control value.
4. The integrated circuit of claim 1 , wherein the first component is a bandgap reference and the reference value is a reference voltage.
5. The integrated circuit of claim 1 , wherein the second component comprises mapping and control logic configured to perform the test algorithm.
6. The integrated circuit of claim 1 ;
wherein the ADC is further configured to receive a specified input signal, and to generate an output code based on the specified input signal in accordance with the reference value.
7. The integrated circuit of claim 6 further comprising a fourth component configured to receive the output code and a specified code corresponding to the external control value, and to generate a control signal based on the output code and the specified code.
8. The integrated circuit of claim 7 , wherein the second component is configured to receive the control signal, and to adjust the reference value according to the control signal.
9. The integrated circuit of claim 8 :
wherein the first component is a bandgap reference;
wherein the second component is a custom logic circuit; and
wherein the fourth component is one of:
a subtractor, wherein the control signal represents a difference between the output code and the specified code; and
a comparator, wherein the control signal indicates whether the output code is less than or equal to the specified code.
10. The integrated circuit of claim 9 ;
wherein the reference value is a reference voltage;
wherein the specified input signal is a known voltage;
wherein the external control value represents a desired reference voltage;
wherein the output code is a numeric representation of the known voltage in accordance with the reference voltage; and
wherein the specified code is a numeric representation of the known voltage in accordance with the desired reference voltage.
11. The integrated circuit of claim 9 , wherein the ADC is comprised in a temperature measurement system configured on the integrated circuit, wherein in adjusting the reference value the custom logic circuit operates to calibrate the temperature measurement system.
12. The integrated circuit of claim 9 ;
wherein if the fourth component is a subtractor then the trimming is completed when the difference between the output code and the specified code has reached a specified value.
13. The integrated circuit of claim 9 ;
wherein if the fourth component is a comparator then the trimming is completed when the output code and the specified code have the same value.
14. The integrated circuit of claim 1 , wherein the test algorithm implements a Remainder Method, wherein control of the trimming is performed based on a magnitude of a remainder from a subtraction of two digital values;
wherein a first of the digital values is a result of a temperature conversion and the second of the digital values is a target value for the temperature conversion.
15. The integrated circuit of claim 1 , wherein the test algorithm implements a Successive Approximation Method.
16. The integrated circuit of claim 1 , wherein the tester apparatus is configured to poll the second component to determine whether the trimming has been completed.
17. The integrated circuit of claim 1 , wherein the second component is operable to provide a feedback signal to the tester apparatus indicating that the trimming has been completed.
18. The integrated circuit of claim 17 , wherein the trimming is performed within a specified amount of time.
19. A method comprising:
generating a reference value, wherein said generating is performed by a first component configured on an integrated circuit;
receiving an external control value;
executing a test algorithm using the external control value, wherein said executing is performed by a second component configured on the integrated circuit; and
trimming the first component according to the test algorithm, thereby adjusting the reference value to substantially match the external control value;
wherein said executing is operable to begin in response to receiving a start signal from a tester apparatus configured to perform testing on the integrated circuit; and
wherein said executing comprises controlling the trimming based on a magnitude of a remainder from a subtraction of two digital values, wherein a first of the digital values is a result of a temperature conversion performed using the reference value, and the second of the digital values is a target value for the temperature conversion.
20. The method of claim 19 , further comprising providing the reference value to a third component configured on the integrated circuit, wherein the third component is configured to operate in accordance with the reference value, and is operable to perform a specified function of the integrated circuit.
21. The method of claim 19 , wherein the first component is a bandgap reference and the reference value is a reference voltage.
22. The method of claim 19 , wherein said executing comprises controlling the trimming based on multiple temperature conversions, according to a Successive Approximation Method.
23. The method of claim 19 , wherein said executing comprises controlling one or more trim control bits, wherein the one or more trim control bits are configured to determine the scope and size of said trimming.
24. The method of claim 23 , further comprising generating a model signal based on the external control value.
25. The method of claim 24 , wherein said controlling comprises setting the one or more trim control bits to a nominal value upon staffing said executing.
26. The method of claim 25 , wherein said controlling further comprises:
generating an output signal based on the reference value;
comparing the output signal and the model signal, thereby obtaining a difference output; and
adjusting the trim control bits according to the difference output.
27. The method of claim 26 , wherein said generating, said comparing, and said adjusting are performed a plurality of times until said adjusting has been performed a specified number of times.
28. The method of claim 26 , wherein said generating, said comparing, and said adjusting are performed a plurality of times until the difference output has reached a specified value.
29. The method of claim 24 , wherein said controlling comprises setting an index to an initial value, wherein for each value of the index, the index identifies a respective one of the trim control bits.
30. The method of claim 29 , wherein said controlling further comprises performing a control sequence;
wherein the control sequence comprises:
setting the respective one of the trim control bits identified by the index;
generating an output signal based on the reference value;
comparing the output signal and the model signal, thereby determining if the output signal is less than or equal to the model signal;
if the output signal is less than the model signal, decreasing a present value of the index by 1; and
if the output signal is greater than the model signal, decreasing a present value of the index by 1 and resetting the respective one of the trim control bits identified by the index.
31. The method of claim 30 , wherein the control sequence is performed a plurality of times until the output signal is equal to the model signal.
32. The method of claim 30 , wherein the control sequence is performed a plurality of times until the present value of the index is 0.
33. The method of claim 19 , wherein said trimming comprises cutting fuses and leaving fuses uncut.
34. The method of claim 19 , wherein said trimming comprises programming a memory element.
35. The method of claim 34 , wherein the memory element is a one time programmable memory element.
36. A system comprising:
an integrated circuit, wherein the integrated circuit comprises:
a bandgap reference operable to generate a reference voltage;
an ADC configured to use the reference voltage to determine a voltage range of an input signal converted by the ADC; and
a control logic circuit operable to execute a test algorithm configured to control a trimming of the bandgap reference to adjust the reference voltage according to an external control value and an output value generated from a specified input signal by the ADC; and
a tester coupled to the integrated circuit and configured to perform testing on the integrated circuit;
wherein the control logic circuit is operable to begin executing the test algorithm in response to receiving a start signal from the tester.
37. The system of claim 36 , wherein the integrated circuit further comprises a temperature measurement system, wherein the ADC is configured in the temperature measurement system, and wherein in adjusting the reference voltage, the control logic circuit operates to calibrate the temperature measurement system.
38. An integrated circuit comprising:
a first component operable to generate a reference value; and
a second component operable to execute a test algorithm configured to control a trimming of the first component according to an external control value to adjust the reference value;
wherein the second component is operable to begin executing the test algorithm in response to receiving a start signal from a tester apparatus configured to perform testing on the integrated circuit;
wherein the test algorithm implements a Remainder Method, wherein control of the trimming is performed based on a magnitude of a remainder from a subtraction of two digital values; and
wherein a first of the digital values is a result of a temperature conversion performed using the reference value, and the second of the digital values is a target value for the temperature conversion.