Hysterisis management for delay line
View Patent ↗A method and apparatus for managing hysterisis in a delay line. In one embodiment, an integrated circuit includes a delay line. A selection circuit is coupled to an input of the delay line. The selection circuit includes two inputs: a first input coupled to convey a signal such as a data signal or a data strobe signal, while the second input is coupled to convey a dummy clock signal. Control logic is coupled to monitor activity within the delay line. Upon detecting a lack of activity for a predetermined time period, the control logic is configured to cause the selection circuit to allow the dummy clock signal to be conveyed to the input of the delay line.
1. An integrated circuit comprising:
a delay line;
a selection circuit coupled to the delay line, the selection circuit having a first input and second input and an output coupled to a delay line input, wherein the first input is coupled to receive a first signal and wherein the second input of the selection circuit is coupled to convey a dummy clock signal; and
control logic coupled to the delay line, wherein the control logic is configured to monitor activity in the delay line, and responsive to detecting a lack of activity for a predetermined time, to configure the selection circuit to convey the dummy clock signal to the input of the delay line by selecting the second input.
2. The integrated circuit as recited in claim 1 , wherein the control logic is configured to monitor the first input of the selection circuit and to select the first input responsive to detecting activity on the first input.
3. The integrated circuit as recited in claim 2 , wherein the first input of the selection circuit is coupled to convey a data strobe signal to the delay line input.
4. The integrated circuit as recited in claim 2 , wherein the first input of the selection circuit is coupled to convey a data signal to the delay line input.
5. The integrated circuit as recited in claim 1 , wherein the delay line is a programmable delay line.
6. The integrated circuit as recited in claim 5 , wherein the control logic is configured to select a delay time for the delay line.
7. The integrated circuit as recited in claim 1 , wherein the integrated circuit is fabricated using a silicon-on-insulator process.
8. The integrated circuit as recited in claim 1 further comprising a demultiplexer coupled to an output of the delay line, wherein the demultiplexer includes a first output and a second output, and wherein the second output is coupled to convey the dummy clock signal, and wherein the control logic is configured to select the second output responsive to detecting the lack of activity on the delay line for the predetermined period of time.
9. The integrated circuit as recited in claim 1 , wherein the control logic is configured to convey a selection signal to the selection circuit in order to select the first signal to be conveyed to the input of the delay line responsive to detecting activity on the first input.
10. A method comprising:
monitoring activity in a delay line, wherein the delay line is coupled to receive a first signal or a second signal via a selection circuit, wherein the second signal is a dummy clock signal;
configuring the selection circuit to convey the dummy clock signal to an input of the delay line responsive to detecting a lack of activity in the delay line for a predetermined period of time.
11. The method as recited in claim 10 , wherein said monitoring activity in the delay line comprises monitoring activity on the first input of the selection circuit.
12. The method as recited in claim 11 , wherein the first signal is a data strobe signal.
13. The method as recited in claim 11 , wherein the first signal is a data signal.
14. The method as recited in claim 11 further comprising configuring the selection circuit to convey the first signal to the input of the delay line responsive to detecting activity on the first input of the selection circuit.
15. The method as recited in claim 10 , wherein the delay line is a programmable delay line.
16. The method as recited in claim 15 further comprising control logic selecting a delay time for the delay line.
17. The method as recited in claim 10 , wherein the delay line and the control logic are implemented on an integrated circuit fabricated using a silicon-on-insulator process.
18. A system comprising:
at least one integrated circuit, wherein the integrated circuit includes:
a delay line;
a selection circuit coupled to the delay line, the selection circuit having a first input and second input and an output coupled to a delay line input, wherein the first input is coupled to receive a first signal and wherein the second input of the selection circuit is coupled to convey a dummy clock signal; and
control logic coupled to the delay line, wherein the control logic is configured to monitor activity in the delay line, and responsive to detecting a lack of activity for a predetermined time, to configure the selection circuit to convey the dummy clock signal to the input of the delay line by selecting the second input.