Method for forming step channel of semiconductor device

1. A method for forming a step channel of a semiconductor device, comprising the steps of:

(a) forming a hard mask layer pattern for defining a step channel region on a semiconductor substrate;

(b) forming a spacer on a sidewall of the hard mask layer pattern; and

(c) simultaneously etching the spacer and a predetermined thickness of the semiconductor substrate using the hard mask layer pattern as an etching mask to form the step channel region having a sloped profile,

wherein during the etching process for the spacer and the semiconductor substrate, a portion of the spacer is etched while the remaining portion of the spacer is used as an etching mask.

2. The method according to claim 1 , wherein the hard mask layer pattern is selected from the group consisting of a nitride film, a tungsten film, a titanium film, a titanium nitride film and combinations thereof.

3. The method according to claim 1 , wherein the predetermined thickness of the semiconductor substrate is substantially the same as that of the hard mask layer pattern.

4. The method according to claim 1 , wherein the spacer comprises one of a polysilicon layer and an oxide film.

5. The method according to claim 1 , wherein the etching process in the step (c) is performed via a dry-etching method having the same etch rate for the spacer and the semiconductor substrate.

6. The method according to claim 1 , further comprising removing the hard mask layer pattern using a wet-etching method.

7. A method for forming a step channel of a semiconductor device, comprising the steps of:

(a) forming a stacked structure of an etch barrier oxide film pattern and a hard mask layer pattern on a semiconductor substrate, the stacked structure defining a step channel region;

(b) forming a spacer on a sidewall of the stacked structure; and

(c) simultaneously etching the spacer, the hard mask layer pattern and a predetermined thickness of the semiconductor substrate using the etch barrier oxide film pattern as an etching mask to form the step channel region having a sloped profile,

wherein during the etching process for the spacer, the hard mask layer pattern and the semiconductor substrate, a portion of the spacer is etched while the remaining portion of the spacer is used as an etching mask.

8. The method according to claim 7 , wherein the etch barrier oxide film pattern is selected from the group consisting of a high temperature oxidation (“HTO”) film, a tetra-ethyl-ortho-silicate (“TEOS”) film, an undoped silicate glass (“USG”) film, a boro phosphor silicate glass (“BPSG”) film and combinations thereof.

9. The method according to claim 7 , wherein the hard mask layer pattern and the spacer comprise a polysilicon layer, respectively.

10. The method according to claim 7 , wherein the predetermined thickness of the semiconductor substrate is substantially the same as that of the stacked structure.

11. The method according to claim 7 , wherein the etching process of the step (c) is performed via a dry-etching method having the same etch rate for the spacer, the hard mask layer pattern and the semiconductor substrate.

12. The method according to claim 7 , further comprising removing the etch barrier layer pattern using a wet-etching method.