Method of fabricating a non-volatile memory
A method of fabricating a nonvolatile memory is provided. The method includes forming a bottom dielectric layer, a charge trapping layer, a top dielectric layer and a conductive layer on the substrate sequentially. Portions of conductive layer, top dielectric layer, charge trapping layer and bottom dielectric layer are removed to form several trenches. An insulation layer is formed in the trenches to form a plurality of isolation structures. A plurality of word lines are formed on the conductive layer and the isolation structures. By using the word lines as a mask, portions of bottom dielectric layer, charge trapping layer, top dielectric layer, conductive layer and isolation structures are removed to form a plurality of devices. The bottom oxide layer has different thickness on the substrate so that these devices can be provided with different performance. These devices serve as memory cells with different character or devices in periphery region.
1. A method for fabricating nonvolatile memory device,
comprising:
providing a substrate, having at least a memory cell region and a periphery circuit region;
forming a first bottom dielectric layer over the memory cell region, and a second bottom dielectric layer over the periphery circuit region, a thickness of the second bottom dielectric layer is greater than a thickness of the first bottom dielectric layer;
forming a charge trapping layer over the substrate;
forming a top dielectric layer over the charge trapping layer;
forming a conductive layer over the top dielectric layer;
forming a patterned mask layer over the conductive layer;
removing portions of the conductive layer, the top dielectric layer, the charge trapping layer, the first bottom dielectric layer, the second bottom dielectric layer and the substrate using the patterned mask layer as a mask, to form a first gate electrode structure at the memory cell region and a second gate electrode structure at the periphery circuit region and a plurality of trenches in the substrate;
filing an insulation layer into the trench; and
removing the patterned mask layer and a portion of the insulation layer until the conductive layer is exposed, so as to form the device isolation structure; and
forming source/drain regions adjacent to the first gate electrode structure and the second gate electrode structure.
2. The method of claim 1 , wherein the step of forming the first bottom dielectric layer over the memory cell region, and the second bottom dielectric layer over the periphery circuit region comprises:
forming a third dielectric layer over the substrate;
forming a first patterned photoresist layer over the third dielectric layer;
using the first patterned photoresist layer as a mask to remove a portion of the third dielectric layer at the memory cell region;
removing the first patterned photoresist layer; and
forming the first bottom dielectric layer over the substrate, wherein the first dielectric layer and the third dielectric layer on the periphery circuit region form the second dielectric layer.
3. The method of claim 2 , wherein formation of the third dielectric layer comprises thermal oxidation.
4. The method of claim 1 , wherein a material constituting the first bottom dielectric layer, the second bottom dielectric layer and the top dielectric layer includes silicon oxide.
5. The method of claim 1 , wherein a material constituting the charge trapping layer includes silicon nitride.
6. The method of claim 1 , wherein a material constituting the conductive layer includes doped polysilicon.
7. The method of claim 1 , wherein the method of removing the patterned mask layer and the portion of the insulation layer comprises chemical mechanical polishing.
8. The method of claim 1 , before filling the insulation layer into the trench, further comprising forming a liner layer on a surface of the trench.
9. The method of claim 8 , wherein the liner layer is formed by thermal oxidation.
10. A method for fabricating nonvolatile memory device, comprising:
providing a substrate, having a plurality of memory cell regions;
forming a bottom dielectric layer over the substrate, having different thickness for different one of the memory cell regions;
forming a charge trapping layer over the bottom dielectric layer,
forming a top dielectric layer over the charge trapping layer;
forming a conductive layer over the top dielectric layer;
removing portions of the conductive layer, the top dielectric layer, the charge trapping layer, the bottom dielectric layer and the substrate to form a plurality of gate electrode structures and a plurality of trenches in the substrate;
filling an insulation layer into the trenches, to form the device isolation structures; and
forming source/drain regions adjacent to the gate electrode structures.
11. The method of claim 10 , wherein the memory cell region comprises a first memory cell region and a second memory cell region, and the steps for forming the bottom dielectric layer comprises:
forming a first dielectric layer over the substrate;
forming a first patterned photoresist layer over the first dielectric layer, wherein the first patterned photoresist layer exposes the first dielectric layer at the first memory cell region;
using the first patterned photoresist layer as a mask to remove the first dielectric layer at the first memory cell region;
removing the first patterned photoresist layer; and
forming a second dielectric layer over the substrate, wherein the second dielectric layer covers the first dielectric layer on the second memory cell region.
12. The method of claim 11 , wherein a method of forming the first dielectric layer and the second dielectric layer includes thermal oxidation.
13. The method of claim 10 , wherein a material constituting the bottom dielectric layer and the top dielectric layer includes silicon oxide.
14. The method of claim 10 , wherein a material constituting the charge trapping layer includes silicon nitride.
15. The method of claim 10 , wherein a material constituting the conductive layer includes doped polysilicon.
16. The method of claim 10 , further including a step of forming a plurality of device isolation structures between the gate electrode structures.