IP Library Granted Patent US 7,262,486
Granted Patent B2
US 7,262,486 · App. 11/154,514 · Granted Aug 28, 2007

SOI substrate and method for manufacturing the same

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Quick Facts
Patent No.
US 7,262,486
App. No.
11/154,514
Granted
Aug 28, 2007
Kind
B2
Abstract

The SOI substrate 1 has a supporting substrate 10 , an insulating layer 20 formed on the supporting substrate 10 and a silicon layer 30 formed on the insulating layer 20 . A through electrode 40 is provided in a device formation region A 1 of the SOI substrate 1 . The through electrode 40 reaches the insulating layer 20 from the silicon layer 30 . Specifically, the through electrode 40 extends to an inner part of the insulating layer 20 originating from a surface of the silicon layer 30 while penetrating the silicon layer 30 . Here, an end face 40 a of the through electrode 40 at the insulating layer 20 side stops inside the insulating layer 20.

Claims (18)

1. An SOI substrate which has an insulating layer and a silicon layer on said insulating layer comprising:

a through electrode reaching said insulating layer from said silicon layer, wherein said insulating layer includes an etch-stop film, and

wherein an end face of said through electrode at said insulating layer side stops inside said insulating layer while said through electrode penetrates through said etch-stop film.

2. The SOI substrate according to claim 1 , wherein said etch-stop film is composed of SiN.

3. The SOI substrate according to claim 2 , wherein said insulating layer includes a silicon oxide film provided on an opposite side of said silicon layer from said etch-stop film.

4. The SOI substrate according to claim 1 , wherein the thickness of said insulating layer is not less than 100 nm and not more than 800 nm.

5. The SOI substrate according to claim 1 , further comprising a polysilicon plug in said silicon layer.

6. The SOI substrate according to claim 5 , wherein said polysilicon plug is in contact with a side face of said through electrode.

7. An SOI substrate which has an insulating layer and a silicon layer on said insulating layer comprising:

a through electrode penetrating said silicon layer and partially embedded in said insulating layer,

wherein said insulating layer includes an etch-stop film, and

wherein an end face of said through electrode at said insulating layer side stops inside said insulating layer while said through electrode penetrates through said etch-stop film.

8. The SOI substrate according to claim 7 , wherein said insulating layer includes a first insulating film and a second insulating film; and

said etch-stop film is disposed between said first insulating film and said second insulating film.

9. The SOI substrate according to claim 8 , wherein said first insulating film and said second insulating film are composed of silicon oxide.

10. The SOI substrate according to claim 9 , wherein said etch-stop film is composed of SiN.

11. The SOI substrate according to claim 7 , further comprising a polysilicon plug provided in said silicon layer.

12. The SOI substrate according to claim 11 , wherein said polysilicon plug is in contact with a side face of said through electrode.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2014
From: RENESAS ELECTRONICS CORPORATION
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 032892/0212 →
CHANGE OF NAME Recorded Nov 11, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025346/0868 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2005
From: KAWANO, MASAYA; TASHIRO, TSUTOMU; KURITA, YOICHIRO
To: NEC ELECTRONICS CORPORATION
Reel/Frame 016705/0373 →