Memory device for reducing leakage current
View Patent ↗Disclosed is a memory device for reducing leakage current generated by a bridge between a word line and a bit line when the memory device is in a waiting mode. The memory device includes: N memory cell blocks each of which includes plurality of memory cell blocks, wherein N represents a natural number; (N+1) sense amp blocks corresponding to the N memory cell blocks; 2N switching blocks connecting the N memory cell blocks to the (N+1) sense amp blocks, respectively; and N controllers for controlling the 2N switching blocks, respectively, wherein the N controllers turn off the 2N switching blocks when the memory device is in a waiting mode, and the N controllers selectively turn on the 2N switching blocks when the memory device is in an operation mode.
1. A memory device for reducing leakage current, the memory device comprising:
N memory cell blocks each of which includes plurality of memory cell blocks, wherein N represents a natural number;
(N+1) sense amp blocks corresponding to the N memory cell blocks;
2N switching blocks connecting the N memory cell blocks to the (N+1) sense amp blocks, respectively;
N controllers for controlling the 2N switching blocks, respectively, each of the controllers having an output; and
N inverters, each inverter of the N inverters having an input coupled to the output of a corresponding one of the N controllers, each inverter of the N inverters having an output that is coupled to a corresponding pair of the 2N switching blocks;
wherein an output signal from each of the N controllers is inverted by a corresponding inverter, and wherein said inverted signal from a controller turns off the 2N switching blocks when the memory device is in a waiting mode, and the N controllers selectively turn on the 2N switching blocks when the memory device is in an operation mode.
2. The memory device as claimed in claim 1 , wherein N word lines connect the memory cells with each other, the N word lines corresponding to the N memory cell blocks respectively, bit lines corresponding to the memory cells connect the N memory cell blocks, the 2N switching blocks and the (N+1) sense amp blocks with each other, and a random i th controller of the N controllers is connected to a (2i−1) th switching block and a 2i.sup.th switching block of the 2N switching blocks, wherein i represents a constant having a value of 1, 2, . . . , N.
3. The memory device as claimed in claim 1 , wherein both a (2k−1) th switching block and a 2k th switching block of the 2N switching blocks are turned on by an k th controller of the N controllers when the memory device is in an operation mode for selecting an k th memory cell block of the N memory cell blocks, wherein k represents a constant having a value of 1, 2, . . . , N.
4. A memory device having a folded bit line structure, the memory device comprising:
N memory cell blocks; and
a first switching block, a sense amp block and a second switching block disposed every between the memory cell blocks,
wherein the first switching block is located between an i th memory cell block and the sense amp block,
the second switching block is located between an (i−1) th memory cell block and the sense amp block,
the first switching block and the second switching block are turned off by a signal from an inverter, said inverter receiving a signal from a controller when the memory device is in a waiting mode, and
only the first switching block adjacent to the i th memory cell block is turned on when the memory device is in an operation mode.
5. The memory device as claimed in claim 4 , wherein when the memory device is in a waiting mode, bit lines of the memory cell block maintain ground voltage.