Metal gate device with reduced oxidation of a high-k gate dielectric
View Patent ↗Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.
1. A method for making a semiconductor device, comprising:
forming a high-k gate dielectric layer on a semiconductor substrate;
forming a metal gate electrode on the high-k gate dielectric layer, the metal gate electrode having a first side and a second side;
forming a first set of spacers on the first and second sides of the metal gate electrode, wherein the first set of spacers is substantially free of oxygen; and
forming a capping layer that is substantially free of oxygen on a top surface of the substrate layer, sides of the first set of spacers, and a top surface of the metal gate electrode.
2. The method of claim 1 , further comprising:
forming a second set of spacers on the capping layer on the first and second sides of the metal gate electrode; and
removing portions of the capping layer on the top surface of the substrate that extend beyond sides of the second set of spacers.
3. The method of claim 1 , further comprising implanting ions into the substrate.
4. The method of claim 3 , wherein the capping layer substantially prevents formation of oxide under the high-k gate dielectric layer during the implantation of ions.
5. The method of claim 3 , wherein the ions are implanted into the substrate through the capping layer.
6. The method of claim 1 , further comprising annealing the substrate after implantation to form source and drain regions.
7. The method of claim 6 , further comprising removing portions of the capping layer, wherein the annealing occurs before removing portions of the capping layer.
8. The method of claim 6 , wherein the capping layer substantially prevents formation of oxide under the high-k gate dielectric layer during the annealing.
9. The method of claim 1 , wherein the capping layer comprises nitride.
10. The method of claim 1 , wherein the capping layer comprises a material selected from the group consisting of 8-12% carbon-doped silicon nitride, stoichiometric silicon nitride and silicon carbide.
11. The method of claim 1 , wherein the capping layer has a thickness below about 75 angstroms.
12. The method of claim 1 , wherein the first set of spacers comprises 8-12% carbon-doped silicon nitride.
13. The method of claim 1 , farther comprising:
prior to forming the capping layer, forming a thin oxide layer between the high-k gate dielectric layer and the semiconductor substrate, wherein the capping layer prevents the thin oxide layer from contacting an oxygen source.