Flash memory cell structure and operating method thereof
View Patent ↗A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.
1. A method of operating a flash memory cell structure, the flash memory cell structure comprising a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region, the substrate having a stacked gate including a control gate, the select gate being formed on the substrate and adjacent to a side of the stacked gate, the first-type doped region being located in the substrate and adjacent to the select gate as a drain, the shallow second-type doped region surrounding the first-type doped region and being short-circuited to the shallow second-type doped region, the doped source being located on a side of the shallow second-type doped region as a source, the method comprising:
applying a high voltage to the control gate, applying a voltage relatively lower than the voltage applied to the control gate to the drain, floating the source, and grounding the select gate in a programming process;
applying a low voltage to the control gate, applying a voltage relatively higher than the voltage applied to the control gate to the select gate, and floating the source and the drain in an erasing process; and
applying a word line voltage to the control gate, applying a voltage relatively lower than the word line voltage to the source, grounding the drain, and applying a power voltage to the select gate in a reading process.
2. The method of claim 1 wherein the flash memory cell structure is a NOR type flash memory cell structure.
3. A method of operating a flash memory cell structure, the flash memory cell structure comprising a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region, the substrate having a stacked gate including a control gate, the select gate being formed on the substrate and adjacent to a side of the stacked gate, the first-type doped region being located in the substrate and adjacent to the select gate as a drain, the shallow second-type doped region surrounding the first-type doped region and being short-circuited to the shallow second-type doped region, the doped source being located on a side of the shallow second-type doped region as a source, the method comprising:
applying a high voltage to the control gate, applying a voltage relatively lower than the voltage applied to the control gate to the source, applying a voltage relatively lower than the voltage applied to the source to the select gate, and grounding the drain in a programming process;
applying a low voltage to the control gate, applying a voltage relatively higher than the voltage applied to the control gate to the drain, floating the source, and grounding the select gate in an erasing process; and
applying a word line voltage to the control gate, applying a voltage relatively lower than the word line voltage to the source, applying a power voltage to the select gate, and grounding the drain in a reading process.
4. The method of claim 3 wherein the operations of the flash memory cell structure are performed in a manner of byte program and byte erase.
5. A method of operating a flash memory cell structure, the flash memory cell structure comprising a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region, the substrate having a stacked gate including a control gate, the select gate being formed on the substrate and adjacent to a side of the stacked gate, the first-type doped region being located in the substrate and adjacent to the select gate as a drain, the shallow second-type doped region surrounding the first-type doped region and being short-circuited to the shallow second-type doped region, the doped source being located on a side of the shallow second-type doped region as a source, the method comprising:
applying a low voltage to the control gate, applying a voltage relatively higher than the voltage applied to the control gate to the drain, floating the source, and grounding the select gate in a programming process;
applying a high voltage to the control gate, applying a voltage relatively lower than the voltage applied to the control gate to the source, floating the drain, and grounding the select gate in an erasing process; and
applying a word line voltage to the control gate, applying a voltage relatively lower than the word line voltage to the source, applying a power voltage to the select gate, and grounding the drain in a reading process.
6. The method of claim 5 wherein the flash memory cell structure is a BiNOR type flash memory cell structure.
7. The method of claim 5 wherein the word line voltage is identical to the power voltage in the reading process.