Flash memory cell and manufacturing method thereof
View Patent ↗A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region. The p-type doped region passes through the junction between the drain region and the p-type pocket doped region but is separated from the spacer by a distance. The contact plug is set up over the drain region and is electrically connected to the p-type doped region.
1. A method of fabricating a flash memory cell, comprising the steps of:
providing a first conductive type substrate;
forming a second conductive type first well region in the substrate;
forming a stacked gate structure over the substrate, wherein the stacked gate structure comprises a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the substrate;
forming a first conductive type pocket doped region in an area of the substrate designated for forming a drain region such that the first conductive type pocket doped region extends to an area underneath the stacked gate structure close to an area designated for forming the a source region;
forming the source region and the drain region in the substrate on each side of the stacked gate structure;
forming a pair of spacers on sidewalls of the stacked gate structure;
forming a first conductive type doped region in the drain region, wherein the first conductive type doped region extends through a junction between the drain region and the first conductive type pocket doped region;
forming an inter-layer dielectric layer over the substrate;
removing a portion of the inter-layer dielectric layer and the spacer to form an contact hole, wherein the contact hole exposes the drain region and the first conductive type doped region such that the first conductive type doped region separates from the spacer by a distance; and
forming a contact plug inside the contact hole, wherein the contact plug is connected to the first conductive type doped region electrically.
2. The method of claim 1 , wherein the distance separating the first conductive type doped region from the spacer is greater than a depth of the drain region.
3. The method of claim 1 , wherein the step of forming the first conductive type doped region in the drain region further comprises:
forming a mask layer that exposes the drain region over the substrate;
forming the first conductive type doped region in the substrate on one side of the drain region using the mask layer and the spacer as a self-aligned mask; and
removing the mask layer.
4. The method of claim 3 , wherein the step of forming the pair of spacers on the sidewalls of the stacked gate structure comprises:
forming first spacers on the sidewalls of the stacked gate structure; and
forming second spacers on the first spacer covered sidewalls of the stacked gate structure.
5. The method of claim 4 , wherein the first spacers and the second spacers are fabricated with materials having different etching selectivity, and the step of removing a portion of the inter-layer dielectric layer and the spacers to form the contact hole comprises removing a portion of the second spacer so that the first conductive type doped region separates from the second spacer by a distance.
6. The method of claim 4 , wherein the step of forming the first conductive type doped region in the drain region comprises using the stacked gate structure with the second spacers thereon as a self-aligned mask in an ion implantation process.
7. The method of claim 1 , wherein the step of forming the first conductive type doped region in the drain region comprises using the stacked gate structure with the spacers thereon as a self-aligned mask in an ion implantation process.
8. The method of claim 3 , wherein the step of forming the first conductive type pocket doped region in an area designated form forming the drain region comprises:
forming a first patterned photoresist layer over the substrate, wherein the first patterned photoresist layer exposes the area in the substrate designated for forming the drain region;
performing a first pocket implantation to form the first conductive type pocket doped region in the designated substrate area for forming the drain region; and
removing the first patterned photoresist layer.
9. The method of claim 8 , wherein the first pocket implantation comprises a tilt angle ion implantation operation.