IP Library Granted Patent US 7,354,851
Granted Patent B2
US 7,354,851 · App. 11/161,080 · Granted Apr 8, 2008

Method for fabricating semiconductor device

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Quick Facts
Patent No.
US 7,354,851
App. No.
11/161,080
Granted
Apr 8, 2008
Kind
B2
Abstract

A method for fabricating a semiconductor device is described. The method includes providing a substrate having a trench therein, and a trench device in the trench. The trench device includes two gate structures disposed on the sidewalls of the trench, a doped region in the substrate between the gate structures and an inter-gate dielectric layer disposed on the surface of the gate structures. A thermal treatment process in a nitrogen-containing ambient is performed to remove the native oxide layer formed on the surface of the doped region. Then, a conductive layer is formed to fill in the trench.

Claims (11)

1. A method for fabricating a semiconductor device, comprising:

forming a trench in a substrate;

performing a first thermal treatment process in a nitrogen-contaming ambient to remove a first native oxide layer comprising silicon dioxide formed on the surface of the trench;

forming a buffer layer in the trench;

performing a second thermal treatment process in a nitrogen-containing ambient to remove a second native oxide layer formed on the surface of the buffer layer, wherein a heating temperature of the first thermal treatment process and the second thermal treatment process is in a range of 700-1000° C.; and

forming the conductive layer to fully fill the trench.

2. The method for fabricating the semiconductor device according to claim 1 , wherein the first and the second thermal treatment processes are rapid thermal anneal process.

3. The method for fabricating the semiconductor device according to claim 1 , wherein a heating time of the first thermal treatment process and the second thermal treatment process is in a range of about 30 -90 seconds.

4. The method for fabricating the semiconductor device according to claim 1 , wherein a material of the conductive layer comprises doped polysilicon.

5. The method for fabricating the semiconductor device according to claim 1 , wherein the step of forming the conductive layer comprises performing chemical vapor deposition (CVD).

6. The method for fabricating the semiconductor device according to claim 1 , wherein a material constituting the buffer layer comprises undoped polysilicon.

Assignments (3)
CHANGE OF NAME Recorded Jul 16, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049757/0536 →
CHANGE OF NAME Recorded Jun 27, 2019
From: POWERCHIP SEMICONDUCTOR CORP.
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 049623/0635 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2005
From: YOUNG, REX; WANG, PIN-YAO
To: POWERCHIP SEMICONDUCTOR CORP.
Reel/Frame 016295/0001 →