IP Library Assignment 049623/0635
Patent Assignment
Reel/Frame 049623/0635

Change of Name

Recorded: 2019-06-27 Pages: 3
Assignor
POWERCHIP SEMICONDUCTOR CORP.
Executed: 2010-08-09
Assignee
POWERCHIP TECHNOLOGY CORPORATION
NO.12, LI-HSIN ROAD 1, HSINCHU SCIENCE PARK,, HSINCHU, TAIWAN
Covered Properties (20)
Method for Fabricating Semiconductor Device
Patent: 7,354,851 →
Application: 11/161,080 →
Publication: US 2006/0166499
Method for Forming Trench Gate Dielectric Layer
Patent: 7,205,217 →
Application: 11/161,177 →
Publication: US 2006/0160306
Non-Volatile Memory and Manufacturing and Operating Method Thereof
Patent: 7,391,078 →
Application: 11/161,398 →
Publication: US 2006/0170038
Flash Memory
Patent: 7,196,371 →
Application: 11/161,994 →
Publication: US 2006/0175654
Non-Volatile Memory Including Assist Gate
Patent: 7,528,438 →
Application: 11/162,035 →
Publication: US 2006/0186459
Method for Manufacturing Semiconductor Devices and Plug
Patent: 7,368,373 →
Application: 11/162,081 →
Publication: US 2006/0183311
Non-Volatile Memory and Fabricating Method and Operating Method Thereof
Patent: 7,274,062 →
Application: 11/162,116 →
Publication: US 2006/0170026
Wafer Measuring Fixture
Patent: 7,431,260 →
Application: 11/162,273 →
Publication: US 2007/0051191
Method of Operating P-Channel Memory
Patent: 7,200,040 →
Application: 11/162,365 →
Publication: US 2006/0215460
Non-Volatile Memory Structure and Method of Fabricating Non-Volatile Memory
Patent: 7,391,073 →
Application: 11/162,497 →
Publication: US 2006/0172491
Non-Volatile Memory Device
Patent: 7,442,998 →
Application: 11/162,648 →
Publication: US 2006/0234446
Semiconductor Device Having Self-Aligned Contact
Patent: 7,612,433 →
Application: 11/162,725 →
Publication: US 2006/0183295
Programmable and Erasable Digital Switch Device and Fabrication Method and Operating Method Thereof
Patent: 7,291,882 →
Application: 11/162,893 →
Publication: US 2006/0231888
Split gate flash memory
Patent: 7,208,796 →
Application: 11/163,223 →
Publication: US 2006/0208307
Method for Forming Buried Doped Region
Patent: 7,465,632 →
Application: 11/163,728 →
Publication: US 2006/0216915
Methods for Determining Tool Assignment Preference and Manufacturing Systems Using the Same
Patent: 7,292,903 →
Application: 11/184,793 →
Publication: US 2006/0195209
Methods and Systems for Semiconductor Defect Detection
Patent: 7,254,759 →
Application: 11/203,236 →
Publication: US 2006/0143550
Method of Piping Defect Detection
Patent: 7,442,561 →
Application: 11/207,895 →
Publication: US 2006/0183256
Inspection Methods for a Semiconductor Device
Patent: 7,132,354 →
Application: 11/213,931 →
Publication: US 2006/0134812
Real-Time Management Systems and Methods for Manufacturing Management and Yield Rate Analysis Integration
Patent: 7,260,444 →
Application: 11/228,361 →
Publication: US 2006/0241802
Related Assignments (4)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name Jul 16, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049757/0536 →
Change of Name Jul 16, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049757/0550 →
Assignment of Assignor's Interest Apr 8, 2020
From: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 052337/0735 →
Assignment of Assignor's Interest Sep 7, 2020
From: POWERCHIP TECHNOLOGY CORPORATION
To: NEXCHIP SEMICONDUCTOR CORPORATION
Reel/Frame 053704/0522 →