Non-volatile memory device
View Patent ↗A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a patterned first inter-layer insulating layer is formed on the substrate to form a first trench and a plurality of second trenches. A conductive layer is formed on the substrate to form a source line in the first trench and conductive lines in the second trenches. A second inter-layer insulating layer is formed on the substrate and then a conductive plug having contact with the drain region is formed in the second inter-layer insulating layer and the first inter-layer insulating layer. Then, a bit line having contact with the conductive plug is formed on the second inter-layer insulating layer.
1. A non-volatile memory, comprising:
a substrate;
a plurality of first memory units disposed on the substrate, wherein the first memory units are separated from one another by a gap and each first memory unit comprises a first composite layer, a first gate and a cap layer sequentially formed over the substrate;
a plurality of second memory units disposed in the gaps between the first memory units, wherein each second memory unit comprises a second composite layer and a second gate sequentially formed over the substrate and the second memory units together with the first memory units form a memory cell column;
a plurality of insulating spacers disposed between the first memory units and the second memory units;
a source region and a drain region disposed in the substrate on the respective sides of the memory cell column;
a first inter-layer insulating layer disposed on the substrate;
a source line disposed in the first inter-layer insulating layer for connecting with the source region;
a plurality of metallic lines disposed in the first inter-layer insulating layer aligned in a direction perpendicular to the memory cell column for connecting with the second gate of the second memory cell units;
a second inter-layer insulating layer disposed on the first inter-layer insulating layer; and
a bit line disposed on the second inter-layer insulating layer for connecting electrically with the drain region through a conductive plug.
2. The non-volatile memory of claim 1 , wherein the material constituting the first gate comprises polycide.
3. The non-volatile memory of claim 1 , wherein the material constituting the second gate comprises doped polysilicon.
4. The non-volatile memory of claim 1 , wherein the material constituting the source line and the metallic lines comprises tungsten.
5. A non-volatile memory, comprising:
a substrate;
a plurality of first memory units disposed on the substrate, wherein the first memory units are separated from one another by a gap and each first memory unit comprises a first composite layer, a first gate and a cap layer sequentially formed over the substrate;
a plurality of second memory units disposed in the gaps between the first memory units, wherein each second memory unit comprises a second composite layer and a second gate sequentially formed over the substrate and the second memory units together with the first memory units form a memory cell column;
a plurality of insulating spacers disposed between the first memory units and the second memory units;
a source region and a drain region disposed in the substrate on the respective sides of the memory cell column;
a first inter-layer insulating layer disposed on the substrate;
a source line disposed in the first inter-layer insulating layer for connecting with the source region;
a second inter-layer insulating layer disposed on the first inter-layer insulating layer;
a third inter-layer insulating layer disposed on the second inter-layer insulating layer;
a first conductive line disposed in the third inter-layer insulating layer for connecting with the source line through a first conductive plug in the second inter-layer insulating layer;
a plurality of second conductive lines disposed in the third inter-layer insulating layer for connecting with the second gates through a plurality of second conductive plugs in the first inter-layer insulating layer and the second inter-layer insulating layer; and
a bit line disposed on the third inter-layer insulating layer for connecting electrically with the drain region trough a third conductive plug.
6. The non-volatile memory of claim 5 , wherein the material constituting the first conductive plug and the second conductive plugs comprises tungsten.
7. The non-volatile memory of claim 5 , wherein the material constituting the first conductive line and the second conductive lines comprises copper-aluminum alloy.
8. The non-volatile memory of claim 5 , wherein the first composite layer and the second composite layer comprises silicon oxide/silicon nitride/silicon oxide composite layers.