Methods and systems for semiconductor defect detection
View Patent ↗A method for semiconductor defect detection, applied to a wafer test in a semiconductor process. A defect test is implemented for generating redundant information. an abnormal test implemented for generating a first FBM. The redundant information is converted to a second FBM. The first and second FBMs are compared, thereby generating a third FBM according to comparison results.
1. A system for semiconductor defect detection, applied to abnormal analysis for a semiconductor component, comprising:
an abnormal test unit, implementing an abnormal test to the semiconductor component for generating a first fail bit map (FBM);
a converting unit, converting redundant information generated through a defect test to a second FBM; and
a comparison unit, comparing the first and second FBMs for generating a third FBM.
2. The system as claimed in claim 1 , wherein the first FBM is an N×N matrix comprising a plurality of failed bits.
3. The system as claimed in claim 2 , wherein the second FBM is an N×N matrix comprising a plurality of failed bits.
4. The system as claimed in claim 3 , wherein the third FBM is an N×N matrix comprising a plurality of failed bits located at corresponding positions in the first and second FBMs based on the XY-plane.
5. A method for semiconductor defect detection, applied to a wafer test in a semiconductor process, comprising:
implementing a defect test for generating redundant information;
implementing an abnormal test for generating a first FBM;
converting the redundant information to a second FBM; and
comparing the first and second FBMs for generating a third FBM.
6. The method as claimed in claim 5 , wherein the first FBM is an N×N matrix comprising a plurality of failed bits.
7. The method as claimed in claim 6 , wherein the second FBM is an N×N matrix comprising a plurality of failed bits.
8. The method as claimed in claim 7 , wherein the third FBM is an N×N matrix comprising a plurality of failed bits located at corresponding positions in the first and second FBMs based on the XY-plane.
9. A semiconductor process implementing a wafer test process, the wafer test process applied to abnormal analysis for a semiconductor component using a method for semiconductor defect detection, the method comprising:
implementing a defect test for generating redundant information;
implementing an abnormal test for generating a first FBM;
converting the redundant information to a second FBM; and
comparing the first and second FBMs for generating a third FBM.
10. The semiconductor process as claimed in claim 9 , wherein the first FBM isan N×N matrix comprising a plurality of failed bits.
11. The semiconductor process as claimed in claim 10 , wherein the second FBM is an N×N matrix comprising a plurality of failed bits.
12. The semiconductor process as claimed in claim 11 , wherein the third. FBM is an N×N matrix comprising a plurality of failed bits located at corresponding positions in the first and second FBMs based on the XY-plane.