Non-volatile memory including assist gate
View Patent ↗A non-volatile memory is provided. An assist gate structure is formed on a substrate such that the width at the bottom of the assist gate structure is greater than the width at the top of the assist gate structure. A floating gate is formed on one side of the assist gate structure and disposed between a word line and the substrate. The width at the bottom of the floating gate is smaller than the width at the top of the floating gate. The word line, the floating gate and the assist gate structure together form a memory unit. A tunneling dielectric layer is formed between the floating gate and the substrate. An inter-gate dielectric layer is formed between the word line, the floating gate and the assist gate structure. Source/drain regions are formed in the substrate on the respective sides of the memory unit.
1. A non-volatile memory, comprising:
a substrate;
an assist gate disposed on the substrate, wherein the bottom portion of the assist gate has a first width and the top portion of the assist gate has a second width, and the first width is greater than the second width;
a gate dielectric layer disposed between the assist gate and the substrate;
a word line disposed on the substrate;
a floating gate disposed on one side of the assist gate and located between the word line and the substrate, wherein the bottom portion of the floating gate has a third width and the top portion of the floating gate has a fourth width, the fourth width is greater than the third width, and the assist gate, the floating gate and the word line together form a memory unit;
a tunneling dielectric layer disposed between the floating gate and the substrate;
an inter-gate dielectric layer disposed between the word line and the floating gate, between the word line and the assist gate and between the assist gate and the floating gate; and
a source/drain region disposed in the substrate on the respective sides of the memory unit.
2. The non-volatile memory of claim 1 , wherein the top portion of the floating gate is higher than the top portion of the assist gate and the top portion of the floating gate also has a sharp corner.
3. The non-volatile memory of claim 1 , wherein the memory further comprises a cap layer disposed between the assist gate and the word line.
4. The non-volatile memory of claim 1 , wherein the first width at the bottom of the assist gate is greater than the third width at the bottom of the floating gate.
5. A non-volatile memory, comprising:
a substrate;
a plurality of assist gates aligned in parallel on the substrate, wherein the bottom portion of each assist gate has a first width and the top portion of each assist gate has a second width, and the first width is greater than the second width;
a plurality of gate dielectric layers disposed between the respective assist gates and the substrate;
a plurality of word lines aligned in parallel on the substrate, wherein the word lines cross over the assist gates;
a plurality of floating gates disposed between various assist gates and located between the word lines and the substrate, wherein the bottom portion of each floating gate has a third width and the top portion of each floating gate has a fourth width, and the fourth width is greater than the third width;
a plurality of tunneling dielectric layers disposed between the respective floating gate and the substrate;
a plurality of inter-gate dielectric layers disposed between the respective word lines and the substrate, between the respective word lines and the assist gates and between the respective assist gates and the floating gates; and
a plurality of source/drain regions disposed in the substrate on one side of the respective assist gates.
6. The non-volatile memory of claim 5 , wherein the top portion of the floating gates are higher than the top portion of the assist gates and the top portion of each floating gates has at least a sharp corner.
7. The non-volatile memory of claim 5 , wherein the memory further comprises a plurality of cap layers disposed between the respective assist gates and the word lines.
8. The non-volatile memory of claim 5 , wherein the first width at the bottom portion of the assist gates is greater than the third width at the bottom of the floating gates.