Non-volatile memory structure and method of fabricating non-volatile memory

1. A method of fabricating a non-volatile memory, comprising:

providing a substrate having a tunneling layer and a floating gate layer thereon;

forming a mask layer on the floating gate layer, wherein the mask layer has at least one opening that exposes a portion of the floating gate layer;

removing a portion of the floating gate layer within the opening to form a sunken region on the surface of the floating gate layer;

forming an inter-gate dielectric layer on the mask layer and the floating gate layer;

forming a control gate layer on the inter-gate dielectric layer within the opening; and

removing the mask layer, the inter-gate dielectric layer on the mask layer, and the floating gate layer under the mask layer.

2. The method of claim 1 , wherein the step of removing a portion of the floating gate layer within the opening to form the sunken region on the surface of the floating gate layer comprises:

performing an oxidation process so that the exposed floating gate layer reacts with oxygen to form an oxide layer, wherein the oxide layer has a material composition different from the floating gate layer; and

removing the oxide layer.

3. The method of claim 2 , wherein the process of removing the oxide layer includes performing a wet etching operation.

4. The method of claim 1 , after forming the control gate layer on the inter-gate dielectric layer but before removing the mask layer and the floating gate layer under the mask layer, further comprising forming an oxide layer on the surface of the exposed control gate layer.

5. The method of claim 4 , wherein the step for forming an oxide layer on the surface of the exposed control gate layer includes performing a thermal oxidation process.

6. The method of claim 1 , after removing the mask layer, the inter-gate dielectric layer on the mask layer, and the floating gate layer under the mask layer, further comprising:

forming a dielectric layer on the sidewalls of the floating gate layer, the inter-gate dielectric layer and the control gate layer; and

forming a conductive layer on the dielectric layer.

7. The method of claim 6 , wherein a material constituting the conductive layer comprises polysilicon or doped polysilicon.

8. The method of claim 1 , wherein the floating gate layer or the control gate layer is composed of polysilicon or doped polysilicon.

9. The method of claim 1 , wherein the mask layer is composed of a material having an etching selectivity different from the floating gate layer.

10. The method of claim 9 , wherein the material comprises silicon nitride.

11. The method of claim 1 , wherein the inter-gate dielectric layer comprises a silicon oxide layer or an oxide/nitride/oxide composite stack.

12. A method of fabricating a non-volatile memory, comprising:

providing a substrate;

forming a tunneling layer on the substrate;

forming a floating gate layer on the tunneling layer;

forming a mask layer on the floating gate layer, wherein the mask layer has at least one first opening that exposes a portion of the floating gate;

removing a portion of the floating gate layer within the first opening to form a sunken region on the surface of the floating gate layer;

forming an inter-gate dielectric layer on the floating gate layer;

forming a control gate layer on the inter-gate dielectric layer to fill up the first opening forming a cap layer on the control gate layer;

removing the mask layer and the floating gate layer under the mask layer to form at least one second opening;

forming a dielectric layer on the sidewalls of the second opening; and

forming a select gate layer within the second opening.

13. The method of claim 12 , wherein the step for removing a portion of the floating gate layer within the first opening to form a sunken region on the surface of the floating gate layer comprises:

performing an oxidation process so that oxygen reacts with the exposed floating gate layer to form an oxide layer, wherein the oxide layer has a material composition different from the floating gate layer; and

removing the oxide layer.

14. The method of claim 13 , wherein the process of removing the oxide layer includes performing a wet etching process.

15. The method of claim 12 , wherein the step for forming the cap layer on the control gate layer comprises performing a thermal oxidation process.

16. The method of claim 12 , wherein the floating gate layer, the control gate layer or the select gate layer is composed of polysilicon or doped polysilicon.

17. The method of claim 12 , wherein the mask layer is composed of a material having an etching selectivity different from the floating gate layer.

18. The method of claim 17 , wherein the material comprises silicon nitride.

19. The method of claim 12 , wherein the inter-gate dielectric layer comprises a silicon oxide layer or an oxide/nitride/oxide composite stack.

20. A non-volatile memory structure, comprising:

a substrate having a tunneling layer thereon;

at least one stack layer disposed on the tunneling layer, wherein the stack layer comprises:

a floating gate layer disposed on the tunneling layer;

a first inter-gate dielectric layer disposed on the floating gate layer;

a control gate layer disposed on the first inter-gate dielectric layer, wherein a contact surface between the floating gate layer and the control gate layer is concave, and the first inter-gate dielectric layer is disposed between the control gate layer and the floating gate layer; and

an oxide layer disposed on the control gate layer;

at least one conductive layer disposed on the tunneling layer and next to the stack layer, wherein the conductive layer contacts the tunneling layer directly; and

at least one second inter-gate dielectric layer disposed on sidewalls of the stack layer and between the conductive layer and the stack layer.

21. The structure of claim 20 , wherein a material of the conductive layer, the floating gate layer and the control gate layer is composed of polysilicon or doped polysilicon.

22. The structure of claim 20 , wherein the first and second inter-gate dielectric layer comprises a silicon oxide layer or an oxide/nitride/oxide composite stack.

23. The structure of claim 20 , wherein the conductive layer is a select gate.