Non-volatile memory and manufacturing and operating method thereof
View Patent ↗A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A plurality of select gate dielectric layers are disposed between the select gates and the substrate. A plurality of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A plurality of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.
1. A non-volatile memory, comprising:
a substrate having a plurality of trenches therein, wherein the trenches are arranged in parallel and extend in a first direction;
a plurality of select gates, each disposed on the substrate between two adjacent trenches respectively;
a plurality of select gate dielectric layers disposed between the select gates and the substrate;
a plurality of composite layers disposed over the surface of the trenches, each composite layer including a charge trapping layer; and
a plurality of word lines arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.
2. The non-volatile memory of claim 1 , wherein each composite layer further comprises a bottom dielectric layer and a top dielectric layer.
3. The non-volatile memory of claim 1 , wherein the material constituting the charge-trapping layer comprises silicon nitride or doped polysilicon.
4. The non-volatile memory of claim 2 , wherein the material constituting the bottom dielectric layer and the top dielectric layer comprises silicon oxide.
5. The non-volatile memory of claim 1 , wherein the composite layers and the word lines disposed thereon constitute a plurality of two-bits memory cells respectively.
6. The non-volatile memory of claim 1 , wherein the material constituting the select gates and the word lines comprises doped polysilicon.
7. The non-volatile memory of claim 1 , wherein the memory further comprises a plurality of bit lines formed in the substrate underneath the select gates when a voltage is applied to the select gates.
8. The non-volatile memory of claim 1 , wherein the composite layers cover the surface of the trenches and the surface of the select gates.