Fin-type field effect transistor
View Patent ↗Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and the drain region. In another embodiment device destruction at high voltages is prevented by ballasting the FinFET. Specifically, resistance is optimized in the fin between the gate and both the source and drain regions (e.g., by increasing fin length, by blocking source/drain implant from the fin, and by blocking silicide formation on the top surface of the fin) so that the FinFET is operable at a predetermined maximum voltage.
1. A fin-type field effect transistor comprising:
a source region;
a drain region;
a semiconductor fin that extends from said source region to said drain region; and
a gate conductor adjacent said semiconductor fin between said source region and said drain region,
wherein a first resistance of said semiconductor fin between said source region and said gate conductor is less than a second resistance of said semiconductor fin between said gate conductor and said drain region,
wherein a first capacitance between said source region and said gate conductor is greater than a second capacitance between said gate conductor and said drain region,
wherein said gate conductor is equidistance between said source region and said drain region,
wherein said semiconductor fin further comprises:
a first portion between said gate conductor and said source region; and
a second portion between said gate conductor and said drain region,
wherein each of said first portion and said second portion comprise:
an inner section adjacent said gate conductor; and
an outer section adjacent said inner section,
wherein said inner section is narrower than said outer section and wherein said inner section of said second portion is longer than said inner section of said first portion.
2. The transistor of claim 1 , wherein said inner section of said second portion is at least approximately three times longer than said inner section of said first portion.
3. The transistor of claim 1 , wherein said semiconductor fin further comprises source/drain extension regions between said gate conductor and said source region and between said gate conductor and said drain region.
4. A fin-type field effect transistor comprising:
a source region;
a drain region;
a semiconductor fin that extends from said source region to said drain region; and
a gate conductor adjacent said semiconductor fin between said source region and said drain region,
wherein said semiconductor fin comprises:
a first portion between said source region and said gate conductor, and
a second portion between said gate conductor and said drain region,
wherein said first portion and said second portion each comprise an inner section adjacent said gate conductor and having a same width and a same length such that each said inner section has at least a minimum amount of resistance required to enable said transistor to be operable at a predetermined maximum voltage,
wherein said first portion and said second portion each further comprise an outer section adjacent said inner section, wherein said outer section is wider than said inner section and wherein said same length is greater than approximately three times said same width.
5. The transistor of claim 4 , wherein each said inner section comprises a corresponding top surface devoid of an adjacent silicide layer.
6. The transistor of claim 4 , further comprising dopants in said source region, in said drain region and in said semiconductor fin, wherein a concentration of said dopants in said source region and said drain region is higher than a concentration of said dopants in said semiconductor fin.
7. The structure of claim 4 , further comprising a plurality of said semiconductor fins between said source region and said drain region, wherein said resistance within each of said semiconductor fins protects said structure against thermal run-away and destruction.
8. A fin-type field effect transistor comprising:
a source region;
a drain region, wherein said source and said drain region comprise parallel planes;
a plurality of semiconductor fins that extend from said source region to said drain region; and
a gate conductor adjacent said semiconductor fins between said source region and said drain region,
wherein a first resistance of each of said semiconductor fins between said source region and said gate conductor is less than a second resistance of each of said semiconductor fins between said gate conductor and said drain region,
wherein a first capacitance between said source region and said gate conductor is greater than a second capacitance between said gate conductor and said drain region,
wherein each of said semiconductor fins further comprises:
a first portion between said gate conductor and said source region; and
a second portion between said gate conductor and said drain region,
wherein each of said first portion and said second portion comprise:
an inner section adjacent said gate conductor; and
an outer section adjacent said inner section,
wherein said inner section is narrower than said outer section and wherein said inner section of said second portion is longer than said inner section of said first portion.
9. The transistor of claim 8 , wherein said inner section of said second portion is at least approximately three times longer than said inner section of said first portion.
10. The transistor of claim 8 , wherein said semiconductor fins each further comprise source/drain extension regions between said gate conductor and said source region and between said gate conductor and said drain region.
11. A fin-type field effect transistor comprising:
a source region;
a drain region;
a plurality of semiconductor fins that extend from said source region to said drain region; and
a gate conductor adjacent said semiconductor fins between said source region and said drain region,
wherein each of said semiconductor fins comprises:
a first portion between said source region and said gate conductor, and
a second portion between said gate conductor and said drain region,
wherein said first portion and said second portion each comprise an inner section adjacent to said gate conductor and having a same uniform width and a same length such that each said inner section has at least a minimum amount of resistance required to avoid current run-away and enable said transistor to be operable at a predetermined maximum voltage,
wherein said first portion and said second portion each further comprise an outer section adjacent and wider than said inner section and wherein said same length is greater than approximately three times said same width.
12. The transistor of claim 11 , wherein each said inner section comprises a corresponding top surface devoid of an adjacent silicide layer.
13. The transistor of claim 11 , further comprising dopants in said source region, in said drain region and in said semiconductor fin, wherein a concentration of said dopants in said source region and said drain region is higher than a concentration of said dopants in said semiconductor fin.