Method for fabricating non-volatile memory
View Patent ↗A method of fabricating a non-volatile memory is described. A substrate is provided and a first dielectric layer, an electron trapping layer and a second dielectric layer are sequentially formed thereon. Each of the stacked gate structures includes a first gate and a cap layer having a gap between every two stacked gate structures. An oxide layer is formed on the sidewalls of the first gate. A portion of the second dielectric layer not covered by the stacked gate structures is removed. A third dielectric layer is further formed on the substrate. A second conductive layer is formed over the substrate, and a portion thereof to form second gates. The second gates and the stacked gate structures form a column of memory cells. A source region and a drain region are formed in the substrate adjacent to two sides of the column of memory cells.
1. A fabrication method of a non-volatile memory, the fabrication method of a non-volatile memory comprising:
forming a first dielectric layer over a substrate;
forming a charge trapping layer;
forming a second dielectric layer;
forming a plurality of stacked gate structures above the second dielectric layer, wherein each stacked gate structures further comprises a first gate and every two of the adjacent stacked gate structures comprises a gap there between;
removing the second dielectric layer not covered by the stacked gate structures to expose the charge trapping layer;
forming a third dielectric layer to cover a surface of the stacked gate structures and the exposed surface of the charge trapping layer;
forming a second conducting layer above the substrate;
removing a portion of the second conducting layer to form a plurality of second gates which each fills the gap between the stacked gate structures, and the second gates and the stacked gate structures form a column of memory cells; and
forming a source region and a drain region beside two sides of the column of memory cells in the substrate.
2. The fabrication method for the non-volatile memory as recited in claim 1 , wherein each stacked gate structure further comprises a cap layer disposed above the first gate.
3. The fabrication method for the non-volatile memory as recited in claim 1 , wherein the step of forming the plurality of the stacked gate structures above the second dielectric layer comprises: forming a first conducting layer over the second dielectric layer;
forming an insulating layer above the first conducting layer; and
patterning both the insulating layer and the first conducting layer to form the cap layers and the first gates.
4. The fabrication method for the non-volatile memory as recited in claim 1 further comprises a step of forming a fourth dielectric layer on side walls of the first gate.
5. The fabrication method for the non-volatile memory as recited in claim 4 , wherein the formation of the fourth dielectric layer comprises a thermal oxidation process.
6. The fabrication method for the non-volatile memory as recited in claim 4 , wherein a material constituting the fourth dielectric layer comprises silicon oxide.
7. The fabrication method for the non-volatile memory as recited in claim 1 , where the step for removing the portion of the second dielectric layer not covered by the stacked gate structures comprises a dry etching process.
8. The fabrication method for the non-volatile memory as recited in claim 1 , wherein the step for forming the first dielectric layer comprises of a thermal oxidation process.
9. The fabrication method for the non-volatile memory as recited in claim 1 , wherein the step for forming the charge trapping layer above the first dielectric layer comprises a chemical vapor deposition process.
10. The fabrication method for the non-volatile memory as recited in claim 1 , wherein the step for forming the second dielectric layer above the charge trapping layer comprises a chemical vapor deposition process.
11. The fabrication method for the non-volatile memory as recited in claim 1 , wherein the step for forming the second conducting layer above the substrate comprises performing a chemical vapor deposition process.
12. The fabrication method for the non-volatile memory as recited in claim 1 , wherein the step for removing the portion of the second conducting layer comprises performing a dry etching process or a chemical mechanical polishing process.
13. The fabrication method for the non-volatile memory as recited in claim 1 , wherein the step for forming a source region and drain region comprises an ion implantation process.
14. The fabrication method for the non-volatile memory as recited in claim 1 , wherein a material constituting the first dielectric layer comprises silicon oxide.
15. The fabrication method for the non-volatile memory as recited in claim 1 , wherein a material constituting the charge trapping layer comprises silicon nitride.
16. The fabrication method for the non-volatile memory as recited in claim 1 , wherein a material constituting the second dielectric layer comprises silicon oxide.
17. The fabrication method for the non-volatile memory as recited in claim 1 , wherein a material constituting the third dielectric layer comprises silicon oxide.
18. The fabrication method for the non-volatile memory as recited in claim 1 , where a material constituting the first conducting layer comprises doped polysilicon.
19. The fabrication method for the non-volatile memory as recited in claim 1 , wherein a material constituting the second conducting layer comprises doped polysilicon.