NAND flash memory cell row and manufacturing method thereof
View Patent ↗A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, inter-gate dielectric layer, a tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. Each of the second stacked gate structure has a select gate dielectric layer, a select gate and a second cap layer. The control gate is between each of the first stacked gate structures, and between each of the second stacked gate structures and the adjacent first stacked gate structure. The floating gate is between the control gate and substrate. The inter-gate dielectric layer is disposed between the control and floating gates. The tunnel oxide is between the floating gate and substrate. The doping regions are disposed under the first stacked gate structure, and the source/drain regions are in the exposed substrate.
1. A manufacturing method of a NAND flash memory cell row, comprising:
forming a plurality of doping regions and a plurality of source/drain regions in a substrate, wherein the source/drain regions are disposed at outer sides of the doping regions;
forming a plurality of stacked gate structures on the substrate, wherein some of the stacked gate structures are disposed on the doping regions and each of the stacked gate structures comprises at least an erase gate, and some of the stacked gate structures are disposed at a distance from the doping regions and beside the source/drain regions and each of the stacked gate structures comprises at least a select gate;
forming a tunnel oxide layer on the substrate to cover the substrate, the erase gate and the select gate surface;
forming a plurality of floating gates between the stacked gate structures, wherein a top surface of the floating gates is a concave surface and has a sharp edge, wherein an edge of the concave surface is lower than a top surface of the erase gates;
forming an inter-gate dielectric layer on the floating gates; and
forming a plurality of control gates on the inter-gate dielectric layer.
2. The manufacturing method of NAND flash memory cell row of claim 1 , wherein the step of forming the floating gates between the stacked gate structures comprises:
forming a first conductive layer between the stacked gate structures;
removing a portion of the first conductive layer to make a top surface of the first conductive layer is lower than a top surface of the stacked gate structures;
oxidizing the top surface of the first conductive layer to form an oxide layer on the top surface of the first conductive layer; and
removing the oxide layer to form the floating gates.
3. The manufacturing method of the NAND flash memory cell row of claim 2 , wherein a method of oxidizing the top surface of the first conductive layer comprises a wet oxidation method.
4. The manufacturing method of the NAND flash memory cell row of claim 2 , wherein a method of removing the portion of the first conductive layer comprises an etch back method.
5. The manufacturing method of the NAND flash memory cell row of claim 1 , wherein the step of forming the control gates between the stacked gate structures comprises:
forming a second conductive layer on the substrate; and
removing a portion of the second conductive layer till the top surface of the stacked gate structures are exposed.
6. The manufacturing method of the NAND flash memory cell row of claim 5 , wherein a method of removing the portion of the second conductive layer comprises an etch back method or a chemical mechanical polishing (CMP) method.
7. The manufacturing method of the NAND flash memory cell row of claim 1 , wherein a material of the tunnel oxide layer comprises silicon oxide.
8. The manufacturing method of the NAND flash memory cell row of claim 7 , wherein a method of forming the tunnel oxide layer comprises a thermal oxidation method.
9. The manufacturing method of the NAND flash memory cell row of claim 1 , wherein the inter-gate dielectric layer comprises a material selected from the group consisting of silicon oxide/silicon nitride/silicon oxide, silicon nitride/silicon oxide or silicon oxide/silicon nitride.
10. The manufacturing method of the NAND flash memory cell row of claim 1 , wherein the step of forming the stacked gate structures on the substrate comprises:
forming a first dielectric layer, a third conductive layer, an oxide layer and a second dielectric layer on the substrate sequentially; and
patterning the second dielectric layer, the oxide layer, the third conductive layer and the first dielectric layer so as to form a first cap layer, the erase gate and an erase gate dielectric layer on the doping regions, and to form a second cap layer, a select gate and the select gate dielectric layer at a distance from the doping regions and beside a side of the source/drain regions.
11. The manufacturing method of NAND flash memory cell row of claim 10 , wherein a method of forming the first dielectric layer on the substrate comprises thermal oxidation process.