Non-volatile memory and fabricating method thereof
View Patent ↗A method of fabricating a non-volatile memory is provided. A substrate having a trench therein for forming a trench device is provided. Then, a doped metal silicide layer is formed on the substrate in the trench. A heating process is performed to form a source/drain area in the substrate under the doped metal silicide layer. Thereafter, a first conductive layer is formed on the doped metal silicide layer to fill up the trench.
1. A non-volatile memory, comprising:
a substrate having a trench therein;
a first dielectric layer disposed on sidewalls of the trench and a part of a bottom surface of the trench;
a floating gate disposed on the respective sidewalls of the trench and located on the first dielectric layer;
a control gate disposed in the trench with a top part of the control gate at a level higher than a surface of the substrate;
a second dielectric layer disposed between the floating gate and the control gate and located on the first dielectric layer;
a doped metal silicide layer disposed between the control gate and the substrate; and
a first source/drain region disposed in the substrate underneath the doped metal silicide layer.
2. The non-volatile memory of claim 1 , wherein a material constituting the doped metal silicide layer comprises germanium silicide.
3. The non-volatile memory of claim 1 , wherein the doped metal silicide layer has a thickness between about 100 Å–500 Å.
4. The non-volatile memory of claim 1 , wherein a material forming the control gate comprises a metallic substance.
5. The non-volatile memory of claim 1 , wherein the memory further comprises:
a third dielectric layer disposed over the substrate to cover the control gate; and
a conductive layer disposed on the third dielectric layer.
6. The non-volatile memory of claim 5 , wherein the conductive layer is disposed on sidewalls of the control gate above a top surface of the substrate.
7. The non-volatile memory of claim 6 , wherein the memory further comprises a second source/drain region disposed in the substrate an respective sides of the conductive layer.
8. The non-volatile memory of claim 1 , wherein a material constituting the floating gate comprises doped polysilicon.
9. The non-volatile memory of claim 1 , wherein a material constituting the first dielectric layer comprises silicon oxide (SiO 2 ).
10. The non-volatile memory of claim 1 , wherein a material constituting the second dielectric layer comprises silicon oxide.