Method of fabricating non-volatile memory

1. A method of fabricating a non-volatile memory, comprising:

providing a substrate with a memory cell region and a peripheral circuit region, wherein a plurality of first stacked gate structures formed on the memory cell region of the substrate and a stacked structure formed on the peripheral circuit region of the substrate;

forming a conductive layer over the substrate and etching back the conductive layer to form a plurality of gates between the first stacked gate structures and produce a memory cell row, and forming a plurality of conductive spacers on the sidewalls of the memory cell row and the stacked structure;

forming a patterned mask layer over the substrate, wherein the patterned mask layer covers at least the memory cell row and the conductive spacers; and

patterning the stacked structure to form a plurality of second stacked gate structures on the peripheral circuit region.

2. The method of claim 1 , further comprises forming a plurality of source/drain regions in the substrate on the respective sides of the memory cell row and the second stacked gate structures.

3. The method of claim 2 , wherein the step of forming the source/drain region comprises performing an ion implant process.

4. The method of claim 1 , further comprises forming a plurality of dielectric layer on the sidewalls of the first stacked gate structures and the stacked structure before forming the conductive layer.

5. The method of claim 4 , wherein the material constituting the dielectric layer comprises silicon oxide.

6. The method of claim 1 , wherein each stacked gate structure comprises a pad conductive layer, a conductive layer and a patterned cap layer.

7. The method of claim 1 , wherein the stacked structure comprises a pad conductive layer, a conductive layer and a patterned cap layer.

8. The method of claim 1 , wherein the material constituting the conductive layer comprises doped polysilicon.

9. A method of fabricating a non-volatile memory, comprising the steps of:

providing a substrate with a memory cell region and a peripheral circuit region, wherein a tunneling dielectric layer, a charge-trapping layer and a barrier dielectric layer are formed in sequence on the memory cell region of the substrate and a gate oxide layer is formed on the peripheral circuit region of the substrate;

forming a pad conductive layer on the substrate;

forming a device isolation structure in the substrate to define a plurality of first active region on the memory cell region and a second active region on the peripheral circuit region;

forming a plurality of first memory units on the memory cell region and a stacked structure that covers at least the second active region on the peripheral circuit region;

forming a first conductive layer over the substrate and etching back the first conductive layer to form a plurality of second memory units between the first memory units and produce a memory cell row, and forming a plurality of conductive spacers on the respective sidewalls of the memory cell row and the stacked structure;

forming a patterned mask layer on the substrate, wherein the patterned mask layer covers at least the memory cell row and the conductive spacers;

patterning the stacked structure to form a stacked gate structure on the second active region on the peripheral circuit region; and

forming a plurality of source/drain regions in the substrate on the respective sides of the memory cell row and the stacked gate structures.

10. The method of claim 9 , wherein the step of forming the device isolation structure comprises:

forming a cap layer over the pad conductive layer;

forming a plurality of openings through the cap layer, the pad conductive layer, the barrier dielectric layer, the charge-trapping layer, the tunneling dielectric layer and a portion of the substrate on the memory cell region and the pad conductive layer, the gate oxide layer and a portion of the substrate on the peripheral circuit region;

depositing dielectric material into the openings, and

removing the cap layer and a portion of the dielectric material layer.

11. The method of claim 9 , wherein the step of forming the first memory units and the stacked structure comprises:

forming a second conductive layer over the pad conductive layer; and

defining the second conductive layer and the pad conductive layer.

12. The method of claim 9 , wherein the step of forming the second memory cell units comprises:

forming a composite dielectric layer on the substrate; and

forming a third conductive layer between the first memory units.

13. The method of claim 12 , wherein the composite dielectric layer comprises an oxide/nitride/oxide composite stacked layer.

14. The method of claim 9 , wherein the material constituting the tunneling dielectric layer comprises silicon oxide.

15. The method of claim 9 , wherein the step of forming the tunneling dielectric layer comprises performing a thermal oxidation process.

16. The method of claim 9 , wherein the step of forming the charge-trapping layer comprises performing a chemical vapor deposition process.

17. The method of claim 9 , wherein the material constituting the charge-trapping layer comprises silicon nitride or doped polysilicon.

18. The method of claim 9 , wherein the step of forming the barrier dielectric layer comprises performing a chemical vapor deposition process.

19. The method of claim 9 , wherein the material constituting the barrier dielectric layer comprises silicon oxide.

20. The method of claim 9 , wherein the step of forming the gate oxide layer comprises performing a wet oxidation process.

21. The method of claim 9 , wherein the material constituting the gate oxide layer comprises silicon oxide.

22. The method of claim 9 , wherein the material constituting the pad conductive layer comprises doped polysilicon.