Resistive memory device with improved data retention
In the present method of programming a memory device from an erased state, the memory device includes first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrodes. In the programming method, (i) an electrical potential is applied across the first and second electrodes from higher to lower potential in one direction to reduce the resistance of the memory device, and (ii) an electrical potential is applied across the first and second electrodes from higher to lower potential in the other direction to further reduce the resistance of the memory device.
1. A method of programming a memory device, the memory device comprising first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrodes, the method comprising:
applying a first electrical potential across the first and second electrodes to reduce the resistance of the memory device, and
applying a second electrical potential across the first and second electrodes to further reduce the resistance of the memory device, wherein the first electrical potential is applied from higher to lower potential in the direction from the first electrode to the second electrode, and wherein the second electrical potential is applied from higher to lower potential in the direction from the second electrode to the first electrode.
2. The method of claim 1 wherein the second electrical potential is different in magnitude from the first electrical potential.
3. The method of claim 2 wherein the second electrical potential is lower in magnitude than the first electrical potential.
4. A method of programming a memory device, the memory device comprising first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrodes, the method comprising:
applying a first electrical potential across the first and second electrodes from higher to lower potential in the direction from the first electrode to the second electrode, and
applying a second electrical potential across the first and second electrodes from higher to lower potential in the direction from the second electrode to the first electrode to reduce the resistance of the memory device.
5. The method of claim 4 wherein application of the first electrical reduces the resistance of the memory device.
6. The method of claim 5 wherein application of the second electrical potential further reduces the resistance of the memory device.
7. The method of claim 6 wherein the second electrical potential is different in magnitude from the first electrical potential.
8. The method of claim 7 wherein the second electrical potential is lower in magnitude than the first electrical potential.
9. A method of programming a memory device, the memory device comprising a first electrode, a passive layer on and in contact with the first and second electrodes, an active layer on and in contact with the first and second electrodes, and a second electrode on and in contact with then active layer, the method comprising:
applying a first electrical potential across the first and second electrodes from higher to lower potential in the direction from the first electrode to the second electrode to reduce the resistance of the memory device, and
applying a second electrical potential across the first and second electrodes from higher to lower potential in the direction from the second electrode to the first electrode to further reduce the resistance of the memory device.
10. The method of claim 9 wherein the second electrical potential is different in magnitude from the first electrical potential.
11. The method of claim 10 wherein the second electrical potential is lower in magnitude than the first electrical potential.
12. A method of programming a memory device, the memory device comprising first and second electrodes, and an active layer between the first and second electrodes, the method comprising:
applying a first electrical potential across the first and second electrodes to move electronic charge carriers into the active layer, and
applying a second electrical potential across the first and second electrodes;
wherein the first electrical potential is applied across the first and second electrodes from higher to lower potential in the direction from the first electrode to the second electrode, and the second electrical potential is applied across the first and second electrodes from higher to lower potential in the direction from the second electrode to the first electrode.
13. The method of claim 12 wherein application of the first electrical potential reduces the resistance of the memory device.
14. The method of claim 12 wherein application of the second electrical potential further reduces the resistance of the memory device.
15. The method of claim 12 wherein the application of the second electrical potential moves ions into the active layer.
16. The method of claim 12 wherein application of the first electrical potential reduces the resistance of the memory device, and application of the second electrical potential further reduces the resistance of the memory device.
17. The method of claim 12 and further comprising a plurality of said memory devices making up an array thereof.