IP Library Granted Patent US 7,450,460
Granted Patent B2
US 7,450,460 · App. 11/166,575 · Granted Nov 11, 2008

Voltage control circuit and semiconductor device

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Quick Facts
Patent No.
US 7,450,460
App. No.
11/166,575
Granted
Nov 11, 2008
Kind
B2
Abstract

A voltage control circuit includes capacitors, first switches that are respectively provided to the capacitors and selectively couple the capacitors with a given node, and second switches that are respectively provided between the first switches and the given node and selectively connect the first switches to the given node.

Claims (43)

1. A voltage control circuit comprising:

capacitors;

first switches that are respectively provided to the capacitors and selectively couple the capacitors with a given node; and

second switches that are respectively provided between the first switches and the given node and selectively connect the first switches to the given node;

wherein:

one of the first switches that selectively couples one of the capacitors with the given node is coupled with the given node via a corresponding one of the second switches; and

another one of the first switches that selectively couples another one of the capacitors with the given node is coupled to the given node via one of the second switches associated with said another one of the first switches and the corresponding one of the second switches.

2. The voltage control circuit as claimed in claim 1 , further comprising a control circuit generating second control signals applied to the second switches from first control signals applied to the first switches.

3. The voltage control circuit as claimed in claim 1 , further comprising a control circuit generating second control signals applied to the second switches from first control signals applied to the first switches so that the first and second switches select capacitors to be connected to the given node from among the capacitors.

4. The voltage control circuit as claimed in claim 1 , wherein the capacitors include a capacitor having a minimum capacitance and capacitors having capacitances equal to powers of the minimum capacitance.

5. A voltage control circuit comprising:

capacitors;

first switches that are respectively provided to the capacitors and selectively couple the capacitors with a given node; and

second switches that are respectively provided between the first switches and the given node and selectively connect the first switches to the given node;

wherein each of the first and second switches includes a transistor having a gate that is set at a potential defined by boosting an external voltage.

6. The voltage control circuit as claimed in claim 5 , further comprising a voltage dividing circuit that applies, to the given node, a given voltage obtained by dividing a first potential applied to a first terminal.

7. A voltage control circuit comprising:

capacitors;

first switches that are respectively provided to the capacitors and selectively couple the capacitors with a given node; and

second switches that are respectively provided between the first switches and the given node and selectively connect the first switches to the given node;

further comprising a voltage dividing circuit that applies, to the given node, a given voltage obtained by dividing a first potential applied to a first terminal, wherein the voltage dividing circuit comprises a transistor coupled between the first potential and the given node.

8. A voltage control circuit comprising:

capacitors;

first switches that are respectively provided to the capacitors and selectively couple the capacitors with a given node; and

second switches that are respectively provided between the first switches and the given node and selectively connect the first switches to the given node;

further comprising a reset circuit that resets the given node in response to a reset signal.

9. The voltage control circuit as claimed in claim 8 , wherein the reset circuit comprises a reset transistor that resets the given node in response to a reset signal, wherein the reset transistor is backward-biased in the absence of the reset signal.

10. A voltage control circuit comprising:

capacitors;

first switches that are respectively provided to the capacitors and selectively couple the capacitors with a given node; and

a reset transistor that resets the given node in response to a reset signal,

the reset transistor being back-biased in the absence of the reset signal.

11. The voltage control circuit as claimed in claim 10 , wherein the first switches respectively comprise first transistors having gates to which a gate voltage is applied, the gate voltage being derived from an external voltage and being higher than the external voltage.

12. The voltage control circuit as claimed in claim 10 , wherein the reset transistor has a gate to which a gate voltage is applied, the gate voltage being derived from an external voltage and being higher than the external voltage.

13. A method comprising the steps of:

controlling first switches that are provided for capacitors and selectively connect the capacitors to a given node; and

controlling second switches that are provided between the first switches and the given node and connecting the first switches to the given node;

further comprising a step of back-biasing a reset transistor that resets the given node in response to a reset signal when the reset signal is not applied thereto.

14. The method as claimed in claim 13 , further comprising a step of producing, from a first control signal applied to the first switches, a second control signal applied to the second switches.

15. The method as claimed in claim 13 , further comprising a step of setting gates of transistors included in the first and second switches to a potential defined by boosting an external voltage.

16. A method comprising the steps of:

controlling first switches that are provided for capacitors and selectively connect the capacitors to a given node; and

back-biasing a reset transistor that resets the given node in response to a reset signal when the reset signal is not applied thereto.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036039/0406 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2005
From: YAMADA, SHIGEKAZU
To: SPANSION LLC
Reel/Frame 017000/0161 →