Wafer alignment method
View Patent ↗The present invention relates to a wafer alignment method. The wafer alignment method includes the steps of forming first bonding pads and first wafer alignment marks of a convex shape on predetermined regions of a first semiconductor substrate in which a first device is formed, forming second bonding pads on predetermined regions of a second semiconductor substrate in which a second device is formed so that they correspond to the first bonding pads, and forming second wafer alignment marks of a hall shape on the predetermined regions of the second semiconductor substrate so that they correspond to the wafer alignment marks of the convex shape, disposing a rear surface of the second semiconductor substrate upwardly, so that the first bonding pads of the first semiconductor substrate and the second bonding pads of the second semiconductor substrate correspond to each other, polishing the rear surface of the second semiconductor substrate to form holes of the second wafer alignment marks through which X-rays to be projected later penetrate, aligning the first semiconductor substrate and the second semiconductor substrate so that the X-rays projected from the X-ray projector penetrate the second wafer alignment marks of the second semiconductor substrate and then reach the wafer alignment marks of the first semiconductor substrate through a X-ray sensing device, which has an X-ray projector and an X-ray detector and is adjacent to the rear surface of the second semiconductor substrate, and performing a thermal process on the first semiconductor substrate and the second semiconductor substrate, which are aligned, to electrically connect the first bonding pads and the second bonding pads.
1. A wafer alignment method, comprising the steps of:
forming first bonding pads and first wafer alignment marks of a convex shape on predetermined regions of a first semiconductor substrate in which a first device is formed;
forming second bonding pads on predetermined regions of a second semiconductor substrate in which a second device is formed so that they correspond to the first bonding pads, and forming second wafer alignment marks of a hall shape on the predetermined regions of the second semiconductor substrate so that they correspond to the wafer alignment marks of the convex shape;
disposing a rear surface of the second semiconductor substrate upwardly, so that the first bonding pads of the first semiconductor substrate and the second bonding pads of the second semiconductor substrate correspond to each other;
polishing the rear surface of the second semiconductor substrate, which is disposed upwardly, to form holes of the second wafer alignment marks through which X-rays to be projected later penetrate;
aligning the first semiconductor substrate and the second semiconductor substrate so that the X-rays projected from the X-ray projector penetrate the second wafer alignment marks of the second semiconductor substrate and then reach the wafer alignment marks of the first semiconductor substrate through a X-ray sensing device, which has an X-ray projector and an X-ray detector and is adjacent to the rear surface of the second semiconductor substrate; and
performing a thermal process on the first semiconductor substrate and the second semiconductor substrate, which are aligned, to electrically connect the first bonding pads and the second bonding pads.
2. The wafer alignment method as claimed in claim 1 , wherein the alignment step of the first semiconductor substrate and the second semiconductor substrate, which is performed so that the X-rays projected from the X-ray projector penetrate the second wafer alignment marks of the second semiconductor substrate and then reach the wafer alignment marks of the first semiconductor substrate, is performed by detecting reflected light of the X-rays, which is reflected from the first wafer alignment marks of the convex shape, using the X-ray detector.
3. The wafer alignment method as claimed in claim 1 , wherein the second device is a logic element, and the first device is a memory device.
4. The wafer alignment method as claimed in claim 1 , wherein the first wafer alignment marks are formed to a thickness of about 8000 to 10000 Å in order to facilitate position detection through the projected X-rays.
5. The wafer alignment method as claimed in claim 1 , wherein the first device is a logic element, and the second device is a memory device.