Fan out type wafer level package structure and method of the same

1. A process of fan out type wafer level package, comprising the steps of:

adhering plurality of first dice to a base;

forming a first material layer on said base to fill in a space among plurality of said first dice on said base;

forming a second material layer on said first material layer and said plurality of first dice;

etching a partial region of said second material layer on first pads of said plurality of first dice to form first openings;

forming a first contact conductive layer on said first openings to electrically couple with said first pads, respectively;

forming first conductive lines over said first contact conductive layer within said first opening and said second material layer;

forming a first isolation layer on said first conductive lines and said second material layer;

adhering plurality of second dice to said first isolation layer;

forming a third material layer on said first isolation layer to fill in a space among plurality of said second dice on said first isolation layer;

forming a fourth material layer on said third material layer and plurality of said second dice;

etching a partial region of said fourth material layer on second pads of plurality of said second dice to form second openings;

forming a second contact conductive layer on said second openings to electrically coupling with said second pads, respectively;

removing a partial region of said fourth material layer, said third material layer, and said first isolation layer on said first conductive lines to forming third openings;

filling up said third openings with conductive material;

forming second conductive lines over said second contact conductive layer within said third opening and said fourth material layer, wherein said first die is coupled to said second die through said conductive material to communicate with each other;

forming a second isolation layer on said second conductive lines and said fourth material layer;

removing a partial region of said second isolation layer on said second conductive lines to forming fourth openings; and

welding solder balls on said fourth openings.

2. The process in claim 1 , wherein surfaces of said third material layer and said second plurality of dies are at same level.

3. The process in claim 1 , further comprising a step of sawing said base to isolate packaged dies having one of said first plurality of dies and one of said second plurality of dies.

4. The process in claim 1 , further comprising a step of adhering a second plurality of first passive components to said isolating base among said second plurality of dies onto said first isolation layer before the step of forming said third material layer.

5. The process in claim 1 , wherein said second plurality of dies comprises at least two types of dies.

6. The process in claim 1 , wherein materials of said third material layer and said fourth material layer comprises UV curing type material, heat curing type material, and the combination thereof.

7. The process in claim 1 , further comprising a step of cleaning each surface of said second pads by using plasma etching after the step of etching a partial region of said fourth material layer.

8. The process in claim 1 , wherein said second contact conductive layer comprises Ti, Cu, and the combination thereof.

9. The process in claim 1 , wherein said second conductive lines comprises Ni, Cu, Au, and the combination thereof.

10. The process in claim 1 , wherein said second contact conductive layer and said second conductive lines are formed by a forming method comprising physical method, chemical method, and the combination thereof.

11. The process in claim 1 , wherein the step of welding said solder balls comprises placing said solder balls on said third openings by a screen printing method and joining said solder balls together with surfaces of said second conductive lines by a IR reflow method.