Device and method to reduce simultaneous switching noise
View Patent ↗By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect.
1. A method for reducing simultaneous switching noise, comprising:
reading values of a first state of a first set of bits of a first word;
projecting value of a corresponding second state of each of the first set of bits;
determining a score representative of at least a plurality of binary transitions, each binary transition from the first state to the corresponding second state;
if the score indicates that more than half of the first states of the plurality of binary transitions differ from the corresponding second states, invert the values of the second states and set a designator;
if the score does not indicate that more than half of the first states of the plurality of binary transitions differ from the corresponding second states, reset the designator;
write the second states to a plurality of bits corresponding to the plurality of binary transitions; and
if the designator is set, write the designator to a bit associated with the plurality of bits corresponding to the plurality of binary transitions.
2. The method of claim 1 , further comprising:
reading the second state of each of the plurality of binary transitions;
reading the designator corresponding to the plurality of binary transitions;
inverting the values of the second state, if the designator indicates that the values of the second state were previously inverted.
3. The method of claim 1 , wherein setting the designator comprises matching the designator to the previous designator value and resetting the designator comprises matching the designator to the inverted previous designator value.
4. A device to reduce transient noise in a digital circuit system, comprising:
means for determining a score representative of at least a plurality of binary transitions, each binary transition from a first state to a corresponding second state;
means for inverting the values of the second states if the score indicates that the absolute value of a difference between the number of high to low binary transitions and the number of low to high binary transition in the plurality of binary transitions is greater than the absolute value of a difference between the number of high to high binary transitions and the number of low to low binary transitions;
means for setting a designator if the score indicates the absolute value of the difference between the number of high to low binary transitions and the number of low to high binary transitions in the plurality of binary transitions is greater than the absolute value of the difference between the number of high to high binary transitions and the number of low to low binary transitions; and
means for resetting the designator if the score indicates the absolute value of the difference between the number of high to low binary transitions and the number of low to high binary transitions in the plurality of binary transitions is not greater than the absolute value of the difference between the number of high to high binary transitions and the number of low to low bin transitions.
5. The device of claim 4 , further comprising:
means for reading the second state of each of the plurality of binary transitions;
means for reading the designator corresponding to the plurality of binary transitions;
means for inverting the values of the second state, if the designator indicates that the values of the second state were previously inverted.
6. The method of claim 4 , wherein setting the designator comprises matching the designator to the previous designator value and resetting the designator comprises matching the designator to the inverted previous designator value.