Method for fabricating CMOS image sensor
View Patent ↗A method for fabricating a CMOS image sensor is disclosed, to decrease a dark current, which includes the steps of forming a photodiode area in a semiconductor substrate; forming a plurality of gates including a first gate on the semiconductor substrate, wherein the first gate has one side aligned to the edge of the photodiode area; sequentially forming a first insulating layer and a second insulating layer on an entire surface of the semiconductor substrate; forming a first photoresist, wherein the firs photoresist is patterned so as to expose the upper side of the first gate and the other side of the gate being opposite to one side of the gate; forming a spacer at the other side of the first gate by dry-etching the second insulating layer in state of using the first photoresist as a mask, and forming a silicide blocking layer above the photodiode area; and removing the first photoresist.
1. A method for fabricating a CMOS image sensor comprising:
forming a photodiotic area in a semiconductor substrate;
forming a plurality of gates including a first gate on the semiconductor substrate, wherein the first gate has one side aligned to an edge of the photodiode area;
sequentially forming a first insulating layer and a second insulating layer on an entire surface of the semiconductor substrate;
forming a first patterned photoresist so as to expose an upper side of the first gate and an other side of the first gate opposite to the one side of the first gate;
forming a spacer at the other side of the first gate by dry-etching the second insulating layer using the first patterned photoresist as a mask, and forming a silicide blocking layer above the photodiode area;
removing the first patterned photoresist;
forming a second photoresist covering the photodiode area, the upper side of the first gate and the spacer, after removing the first photoresist;
forming spacers at sides of the plurality of gates other than the first gate by etching-back the first insulating layer using the second photoresist as a mask; and
removing the second photoresist.
2. The method of claim 1 , wherein the first insulating layer comprises a TEOS layer.
3. The method of claim 1 , wherein the second insulating layer comprises a nitride layer.
4. The method of claim 2 , wherein the second insulating layer comprises a nitride layer.
5. The method of claim 1 , wherein forming the spacer at the other side of the first gate comprises dry-etching the second insulating layer and without removing the first insulating layer.
6. The method of claim 5 , wherein forming the spacer at the other side of the first gate also forms the suicide blocking layer above the photodiode area.
7. The method of claim 5 , wherein the second insulating layer comprises a nitride layer.
8. The method of claim 5 , wherein the first insulating layer comprises a TEOS layer.
9. The method of claim 8 , wherein the second insulating layer comprises a nitride layer.
10. The method of claim 1 , wherein the first gate comprises a transfer gate adjacent to the photodiode area.
11. The method of claim 10 , wherein the other gates of the plurality of gates comprise a reset gate, a drive gate and a select gate.
12. The method of claim 1 , wherein etching back the second insulating layer exposes the other gates of the plurality of gates.
13. The method of claim 12 , further comprising performing a silicide process using the silicide blocking layer as a mask.